| /dports/emulators/qemu42/qemu-4.2.1/roms/u-boot/arch/arm/lib/ |
| H A D | cache-cp15.c | 137 reg |= TTBCR_ORGN0_WBNWA | TTBCR_IRGN0_WBNWA; in mmu_setup()
|
| /dports/emulators/qemu5/qemu-5.2.0/roms/u-boot/arch/arm/lib/ |
| H A D | cache-cp15.c | 137 reg |= TTBCR_ORGN0_WBNWA | TTBCR_IRGN0_WBNWA; in mmu_setup()
|
| /dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot/arch/arm/lib/ |
| H A D | cache-cp15.c | 137 reg |= TTBCR_ORGN0_WBNWA | TTBCR_IRGN0_WBNWA; in mmu_setup()
|
| /dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot/arch/arm/lib/ |
| H A D | cache-cp15.c | 137 reg |= TTBCR_ORGN0_WBNWA | TTBCR_IRGN0_WBNWA; in mmu_setup()
|
| /dports/sysutils/u-boot-utilite/u-boot-2015.07/arch/arm/cpu/armv7/ls102xa/ |
| H A D | cpu.c | 54 #define TTBCR_IRGN0_WBNWA (3 << 8) macro
|
| /dports/sysutils/u-boot-tools/u-boot-2020.07/arch/arm/lib/ |
| H A D | cache-cp15.c | 139 reg |= TTBCR_ORGN0_WBNWA | TTBCR_IRGN0_WBNWA; in mmu_setup()
|
| /dports/emulators/qemu60/qemu-6.0.0/roms/u-boot/arch/arm/lib/ |
| H A D | cache-cp15.c | 137 reg |= TTBCR_ORGN0_WBNWA | TTBCR_IRGN0_WBNWA; in mmu_setup()
|
| /dports/emulators/qemu42/qemu-4.2.1/roms/u-boot/arch/arm/cpu/armv7/ls102xa/ |
| H A D | cpu.c | 55 #define TTBCR_IRGN0_WBNWA (3 << 8) macro
|
| /dports/emulators/qemu5/qemu-5.2.0/roms/u-boot/arch/arm/cpu/armv7/ls102xa/ |
| H A D | cpu.c | 55 #define TTBCR_IRGN0_WBNWA (3 << 8) macro
|
| /dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/arch/arm/cpu/armv7/ls102xa/ |
| H A D | cpu.c | 61 #define TTBCR_IRGN0_WBNWA (3 << 8) macro
|
| /dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/arch/arm/lib/ |
| H A D | cache-cp15.c | 148 reg |= TTBCR_ORGN0_WBNWA | TTBCR_IRGN0_WBNWA; in mmu_setup()
|
| /dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/arch/arm/cpu/armv7/ls102xa/ |
| H A D | cpu.c | 61 #define TTBCR_IRGN0_WBNWA (3 << 8) macro
|
| /dports/sysutils/u-boot-olinuxino-lime2-emmc/u-boot-2021.07/arch/arm/cpu/armv7/ls102xa/ |
| H A D | cpu.c | 61 #define TTBCR_IRGN0_WBNWA (3 << 8) macro
|
| /dports/sysutils/u-boot-olinuxino-lime2-emmc/u-boot-2021.07/arch/arm/lib/ |
| H A D | cache-cp15.c | 148 reg |= TTBCR_ORGN0_WBNWA | TTBCR_IRGN0_WBNWA; in mmu_setup()
|
| /dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/arch/arm/lib/ |
| H A D | cache-cp15.c | 148 reg |= TTBCR_ORGN0_WBNWA | TTBCR_IRGN0_WBNWA; in mmu_setup()
|
| /dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/arch/arm/lib/ |
| H A D | cache-cp15.c | 148 reg |= TTBCR_ORGN0_WBNWA | TTBCR_IRGN0_WBNWA; in mmu_setup()
|
| /dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/arch/arm/lib/ |
| H A D | cache-cp15.c | 148 reg |= TTBCR_ORGN0_WBNWA | TTBCR_IRGN0_WBNWA; in mmu_setup()
|
| /dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/arch/arm/cpu/armv7/ls102xa/ |
| H A D | cpu.c | 61 #define TTBCR_IRGN0_WBNWA (3 << 8) macro
|
| /dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/arch/arm/cpu/armv7/ls102xa/ |
| H A D | cpu.c | 61 #define TTBCR_IRGN0_WBNWA (3 << 8) macro
|
| /dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/arch/arm/lib/ |
| H A D | cache-cp15.c | 148 reg |= TTBCR_ORGN0_WBNWA | TTBCR_IRGN0_WBNWA; in mmu_setup()
|
| /dports/sysutils/u-boot-firefly-rk3399/u-boot-2021.07/arch/arm/cpu/armv7/ls102xa/ |
| H A D | cpu.c | 61 #define TTBCR_IRGN0_WBNWA (3 << 8) macro
|
| /dports/sysutils/u-boot-sopine/u-boot-2021.07/arch/arm/cpu/armv7/ls102xa/ |
| H A D | cpu.c | 61 #define TTBCR_IRGN0_WBNWA (3 << 8) macro
|
| /dports/sysutils/u-boot-sinovoip-bpi-m3/u-boot-2021.07/arch/arm/cpu/armv7/ls102xa/ |
| H A D | cpu.c | 61 #define TTBCR_IRGN0_WBNWA (3 << 8) macro
|
| /dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/arch/arm/lib/ |
| H A D | cache-cp15.c | 148 reg |= TTBCR_ORGN0_WBNWA | TTBCR_IRGN0_WBNWA; in mmu_setup()
|
| /dports/sysutils/u-boot-a13-olinuxino/u-boot-2021.07/arch/arm/lib/ |
| H A D | cache-cp15.c | 148 reg |= TTBCR_ORGN0_WBNWA | TTBCR_IRGN0_WBNWA; in mmu_setup()
|