1 /* 2 * Copyright © 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the 6 * "Software"), to deal in the Software without restriction, including 7 * without limitation the rights to use, copy, modify, merge, publish, 8 * distribute, sub license, and/or sell copies of the Software, and to 9 * permit persons to whom the Software is furnished to do so, subject to 10 * the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the 13 * next paragraph) shall be included in all copies or substantial portions 14 * of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 19 * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR 20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: 25 * Zhao Yakui <yakui.zhao@intel.com> 26 * 27 */ 28 29 /* 30 * Copyright (c) 2010, The WebM Project authors. All rights reserved. 31 * 32 * An additional intellectual property rights grant can be found 33 * in the file LIBVPX_PATENTS. All contributing project authors may 34 * be found in the LIBVPX_AUTHORS file. 35 * 36 * Redistribution and use in source and binary forms, with or without 37 * modification, are permitted provided that the following conditions are met: 38 39 * Redistributions of source code must retain the above copyright 40 * notice, this list of conditions and the following disclaimer. 41 * 42 * Redistributions in binary form must reproduce the above copyright 43 * notice, this list of conditions and the following disclaimer in 44 * the documentation and/or other materials provided with the distribution. 45 46 * Neither the name of Google, nor the WebM Project, nor the names 47 * of its contributors may be used to endorse or promote products 48 * derived from this software without specific prior written permission. 49 * 50 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 51 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 52 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 53 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 54 * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 55 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 56 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 57 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 58 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 59 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 60 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 61 * 62 */ 63 64 #ifndef __INTEL_HOSTVLD_VP9_INTERNAL_H__ 65 #define __INTEL_HOSTVLD_VP9_INTERNAL_H__ 66 67 #include "media_drv_driver.h" 68 #include <pthread.h> 69 #include <semaphore.h> 70 #include "cmrt_api.h" 71 #include "intel_hybrid_hostvld_vp9.h" 72 #include "intel_hybrid_common_vp9.h" 73 74 // Macro to enable separated loop filter 75 #define SEPERATE_LOOPFILTER_ENABLE 76 77 #define VP9_COEF_BANDS 6 // Middle dimension reflects the coefficient position within the transform. 78 #define VP9_PREV_COEF_CONTEXTS 6 79 #define VP9_UNCONSTRAINED_NODES 3 80 #define VP9_MAX_SEGMENTS 8 81 #define VP9_BLK_SIZE_GROUPS 4 82 #define VP9_MBSKIP_CONTEXTS 3 83 #define VP9_PARTITION_PLOFFSET 4 // number of probability models per block size 84 #define VP9_PARTITION_CONTEXTS (4 * VP9_PARTITION_PLOFFSET) 85 #define VP9_TX_SIZE_CONTEXTS 2 86 #define VP9_TOKEN_CACHE_SIZE 1024 87 #define VP9_MAX_PROB 255 88 89 #define VP9_SEG_PRED_PROBS 3 90 #define VP9_INTER_MODE_CONTEXTS 7 91 #define VP9_SWITCHABLE_FILTERS 3 92 #define VP9_SWITCHABLE_FILTER_CONTEXTS (VP9_SWITCHABLE_FILTERS + 1) 93 #define VP9_INTRA_INTER_CONTEXTS 4 94 #define VP9_COMPOUND_INTER_CONTEXTS 5 95 #define VP9_REF_CONTEXTS 5 96 97 #define VP9_MAX_TILE_ROWS 4 98 #define VP9_MAX_TILE_COLUMNS 64 99 #define VP9_MAX_TILES (VP9_MAX_TILE_ROWS * VP9_MAX_TILE_COLUMNS) 100 101 #define VP9_LOG2_B64_SIZE 6 102 #define VP9_LOG2_B8_SIZE 3 103 #define VP9_LOG2_B4_SIZE 2 104 #define VP9_LOG2_B64_SIZE_IN_B8 (VP9_LOG2_B64_SIZE - VP9_LOG2_B8_SIZE) 105 #define VP9_LOG2_B64_SIZE_IN_B4 (VP9_LOG2_B64_SIZE - VP9_LOG2_B4_SIZE) 106 #define VP9_B64_SIZE (1 << VP9_LOG2_B64_SIZE) 107 #define VP9_B64_SIZE_IN_B8 (1 << VP9_LOG2_B64_SIZE_IN_B8) 108 #define VP9_B64_SIZE_IN_B4 (1 << VP9_LOG2_B64_SIZE_IN_B4) 109 110 #define VP9_MV_CLASS0_BITS 1 111 #define VP9_MV_CLASS0_SIZE (1 << VP9_MV_CLASS0_BITS) 112 #define VP9_MV_OFFSET_BITS (VP9_MV_CLASSES + VP9_MV_CLASS0_BITS - 2) 113 #define VP9_MAX_MV_REF_CANDIDATES 2 114 #define VP9_LOG2_MV_REF_NEIGHBOURS 3 115 #define VP9_MV_REF_NEIGHBOURS (1 << VP9_LOG2_MV_REF_NEIGHBOURS) 116 #define VP9_MV_BORDER (16 << 4) // allow 16 pixels in unit of 1/8th pixel 117 #define VP9_MV_MARGIN (156 << 4) 118 119 120 #define VP9_COMPANDED_MVREF_THRESH 8 121 122 123 // Coefficient token alphabet 124 #define VP9_ZERO_TOKEN 0 /* 0 Extra Bits 0+0 */ 125 #define VP9_ONE_TOKEN 1 /* 1 Extra Bits 0+1 */ 126 #define VP9_TWO_TOKEN 2 /* 2 Extra Bits 0+1 */ 127 #define VP9_THREE_TOKEN 3 /* 3 Extra Bits 0+1 */ 128 #define VP9_FOUR_TOKEN 4 /* 4 Extra Bits 0+1 */ 129 #define VP9_DCT_VAL_CATEGORY1 5 /* 5-6 Extra Bits 1+1 */ 130 #define VP9_DCT_VAL_CATEGORY2 6 /* 7-10 Extra Bits 2+1 */ 131 #define VP9_DCT_VAL_CATEGORY3 7 /* 11-18 Extra Bits 3+1 */ 132 #define VP9_DCT_VAL_CATEGORY4 8 /* 19-34 Extra Bits 4+1 */ 133 #define VP9_DCT_VAL_CATEGORY5 9 /* 35-66 Extra Bits 5+1 */ 134 #define VP9_DCT_VAL_CATEGORY6 10 /* 67+ Extra Bits 14+1 */ 135 #define VP9_DCT_EOB_TOKEN 11 /* EOB Extra Bits 0+0 */ 136 #define VP9_MAX_ENTROPY_TOKENS 12 137 #define VP9_ENTROPY_NODES 11 138 139 #define VP9_DCT_EOB_MODEL_TOKEN 3 /* EOB Extra Bits 0+0 */ 140 141 #define VP9_MAX_LOOP_FILTER 63 142 143 // bit offset of flags 144 #define VP9_SKIP_FLAG 0 145 #define VP9_IS_INTER_FLAG 1 146 147 #define VP9_TKN_TREE_SZ(NUM_LEAFS) (2 * (NUM_LEAFS) - 1) 148 149 #define INTEL_HOSTVLD_VP9_READ_BIT(Prob) Intel_HostvldVp9_BacEngineReadBit(pBacEngine, Prob) 150 #define INTEL_HOSTVLD_VP9_READ_ONE_BIT Intel_HostvldVp9_BacEngineReadSingleBit(pBacEngine) 151 #define INTEL_HOSTVLD_VP9_READ_BITS(Bits) Intel_HostvldVp9_BacEngineReadMultiBits(pBacEngine, Bits) 152 #define INTEL_HOSTVLD_VP9_READ_TREE(Tree) Intel_HostvldVp9_BacEngineReadTree(pBacEngine, Tree) 153 #define INTEL_HOSTVLD_VP9_READ_DWORD(Data) (((Data)[0] << 24) | ((Data)[1] << 16) | ((Data)[2] << 8) | (Data)[3]) 154 155 #define INTEL_VP9_CLAMP(Value, Min, Max) \ 156 ((Value) < (Min) ? (Min) : ((Value) > (Max) ? (Max) : (Value))) 157 158 #define INTEL_VP9_ROUND_POWER_OF_TWO(Value, n) \ 159 (((Value) + (1 << ((n) - 1))) >> (n)) 160 161 #define INTEL_HOSTVLD_VP9_INTRA_MODE_PROB_TREE(p0, p1, p2, p3, p4, p5, p6, p7, p8)\ 162 {\ 163 {-1, p0}, {PRED_MD_DC, 0}, {-1, p1}, {PRED_MD_TM, 0}, {-1, p2}, {PRED_MD_V, 0}, {-1, p3},\ 164 {-2, p4}, {-5, p6}, {PRED_MD_H, 0}, {-1, p5}, {PRED_MD_D135, 0}, {PRED_MD_D117, 0},\ 165 {PRED_MD_D45, 0}, {-1, p7}, {PRED_MD_D63, 0}, {-1, p8}, {PRED_MD_D153, 0}, {PRED_MD_D207, 0}\ 166 } 167 #define INTEL_HOSTVLD_VP9_SEGMENT_PROB_TREE(p0, p1, p2, p3, p4, p5, p6)\ 168 {\ 169 {-1, p0}, {-2, p1}, {-3, p2}, {-4, p3}, {-5, p4}, {-6, p5}, {-7, p6},\ 170 {0, 0}, {1, 0}, {2, 0}, {3, 0}, {4, 0}, {5, 0}, {6, 0}, {7, 0}\ 171 } 172 #define INTEL_HOSTVLD_VP9_PARTITION_PROB_TREE(p0, p1, p2)\ 173 {\ 174 {-1, p0}, {PARTITION_NONE, 0}, {-1, p1}, {PARTITION_HORZ, 0}, {-1, p2},\ 175 {PARTITION_VERT, 0}, {PARTITION_SPLIT, 0}\ 176 } 177 178 typedef enum 179 { 180 VP9_CODED_YUV_PLANE_Y, 181 VP9_CODED_YUV_PLANE_U, 182 VP9_CODED_YUV_PLANE_V, 183 VP9_CODED_YUV_PLANES 184 } INTEL_HOSTVLD_VP9_CODED_YUV_PLANE; 185 186 typedef enum { 187 KEY_FRAME = 0, 188 INTER_FRAME = 1, 189 FRAME_TYPES, 190 } INTEL_HOSTVLD_VP9_FRAME_TYPE; 191 192 typedef enum 193 { 194 BLOCK_4X4 = 0, 195 BLOCK_8X8, 196 BLOCK_16X16, 197 BLOCK_32X32, 198 BLOCK_64X64, 199 BLOCK_8X4 = 5, 200 BLOCK_16X8, 201 BLOCK_32X16, 202 BLOCK_64X32, 203 BLOCK_4X8 = 9, 204 BLOCK_8X16, 205 BLOCK_16X32, 206 BLOCK_32X64, 207 BLOCK_SIZES, 208 BLOCK_INVALID = BLOCK_SIZES 209 } INTEL_HOSTVLD_VP9_BLOCK_SIZE; 210 211 typedef enum 212 { 213 PARTITION_NONE, 214 PARTITION_HORZ, 215 PARTITION_VERT, 216 PARTITION_SPLIT, 217 PARTITION_TYPES, 218 PARTITION_INVALID = PARTITION_TYPES 219 } INTEL_HOSTVLD_VP9_PARTITION_TYPE; 220 221 typedef enum 222 { 223 INTRA = 0, 224 INTER = 1, 225 REF_TYPES 226 } INTEL_HOSTVLD_VP9_PREDICTION_TYPE; 227 228 typedef enum 229 { 230 PRED_MD_DC, 231 PRED_MD_V, 232 PRED_MD_H, 233 PRED_MD_D45, 234 PRED_MD_D135, 235 PRED_MD_D117, 236 PRED_MD_D153, 237 PRED_MD_D207, 238 PRED_MD_D63, 239 PRED_MD_TM, 240 INTRA_MODE_COUNT, 241 PRED_MD_NEARESTMV = INTRA_MODE_COUNT, 242 PRED_MD_NEARMV, 243 PRED_MD_ZEROMV, 244 PRED_MD_NEWMV, 245 INTER_MODE_COUNT = PRED_MD_NEWMV - PRED_MD_TM, 246 MB_MODE_COUNT = INTER_MODE_COUNT + INTRA_MODE_COUNT 247 } INTEL_HOSTVLD_VP9_MB_PRED_MODE; 248 249 typedef enum 250 { 251 TX_4X4 = 0, // 4x4 dct transform 252 TX_8X8 = 1, // 8x8 dct transform 253 TX_16X16 = 2, // 16x16 dct transform 254 TX_32X32 = 3, // 32x32 dct transform 255 TX_SIZES 256 } INTEL_HOSTVLD_VP9_TX_SIZE; 257 258 typedef enum { 259 ONLY_4X4 = 0, 260 ALLOW_8X8 = 1, 261 ALLOW_16X16 = 2, 262 ALLOW_32X32 = 3, 263 TX_MODE_SELECT = 4, 264 TX_MODES = 5, 265 } INTEL_HOSTVLD_VP9_TX_MODE; 266 267 typedef enum 268 { 269 TX_DCT = 0, // DCT in both horizontal and vertical 270 TX_ADST_DCT = 1, // ADST in vertical, DCT in horizontal 271 TX_DCT_ADST = 2, // DCT in vertical, ADST in horizontal 272 TX_ADST = 3, // ADST in both directions 273 TX_LOSSLESS = 4, 274 TX_TYPE_COUNT 275 } INTEL_HOSTVLD_VP9_TX_TYPE; 276 277 typedef enum 278 { 279 SEG_LVL_ALT_Q = 0, // Use alternate Quantizer .... 280 SEG_LVL_ALT_LF = 1, // Use alternate loop filter value... 281 SEG_LVL_REF_FRAME = 2, // Optional Segment reference frame 282 SEG_LVL_SKIP = 3, // Optional Segment (0,0) + skip mode 283 SEG_LVL_MAX = 4 // Number of features supported 284 } INTEL_HOSTVLD_VP9_SEG_LVL; 285 286 // interpolation filter type 287 typedef enum 288 { 289 VP9_INTERP_EIGHTTAP = 0, 290 VP9_INTERP_EIGHTTAP_SMOOTH = 1, 291 VP9_INTERP_EIGHTTAP_SHARP = 2, 292 VP9_INTERP_BILINEAR = 3, 293 VP9_INTERP_SWITCHABLE = 4 294 } INTEL_HOSTVLD_VP9_INTERPOLATION_TYPE; 295 296 typedef enum 297 { 298 VP9_REF_FRAME_NONE = -2, 299 VP9_REF_FRAME_INTRA = -1, 300 VP9_REF_FRAME_LAST = 0, 301 VP9_REF_FRAME_GOLDEN, 302 VP9_REF_FRAME_ALTREF, 303 VP9_REF_FRAME_MAX 304 } INTEL_HOSTVLD_VP9_REF_FRAME, *PINTEL_HOSTVLD_VP9_REF_FRAME; 305 306 typedef enum 307 { 308 VP9_SINGLE_PREDICTION_ONLY = 0, 309 VP9_COMPOUND_PREDICTION_ONLY, 310 VP9_HYBRID_PREDICTION 311 } INTEL_HOSTVLD_VP9_PREDICTION_MODE_TYPE; 312 313 typedef enum 314 { 315 VP9_MV_HORIZONTAL, 316 VP9_MV_VERTICAL, 317 VP9_MV_COMPONENTS 318 } INTEL_HOSTVLD_VP9_MV_COMPONENT; 319 320 typedef enum 321 { 322 VP9_MV_JOINT_ZERO = 0, 323 VP9_MV_JOINT_HNZ_VZ = 1 << VP9_MV_HORIZONTAL, 324 VP9_MV_JOINT_HZ_VNZ = 1 << VP9_MV_VERTICAL, 325 VP9_MV_JOINT_HNZ_VNZ = VP9_MV_JOINT_HNZ_VZ | VP9_MV_JOINT_HZ_VNZ, 326 VP9_MV_JOINTS 327 } INTEL_HOSTVLD_VP9_MV_JOINT_TYPE; 328 329 typedef enum 330 { 331 VP9_MV_CLASS_0 = 0, 332 VP9_MV_CLASS_1 = 1, 333 VP9_MV_CLASS_2 = 2, 334 VP9_MV_CLASS_3 = 3, 335 VP9_MV_CLASS_4 = 4, 336 VP9_MV_CLASS_5 = 5, 337 VP9_MV_CLASS_6 = 6, 338 VP9_MV_CLASS_7 = 7, 339 VP9_MV_CLASS_8 = 8, 340 VP9_MV_CLASS_9 = 9, 341 VP9_MV_CLASS_10 = 10, 342 VP9_MV_CLASSES 343 } INTEL_HOSTVLD_VP9_MV_CLASS_TYPE; 344 345 typedef enum { 346 VP9_MV_CONTEXT_BOTH_ZERO = 0, 347 VP9_MV_CONTEXT_ZERO_PLUS_PREDICTED = 1, 348 VP9_MV_CONTEXT_BOTH_PREDICTED = 2, 349 VP9_MV_CONTEXT_NEW_PLUS_NON_INTRA = 3, 350 VP9_MV_CONTEXT_BOTH_NEW = 4, 351 VP9_MV_CONTEXT_INTRA_PLUS_NON_INTRA = 5, 352 VP9_MV_CONTEXT_BOTH_INTRA = 6, 353 VP9_MV_CONTEXT_INVALID_CASE = 9 354 } INTEL_HOSTVLD_VP9_MV_CONTEXT; 355 356 typedef struct _INTEL_HOSTVLD_VP9_PARTITION_PROBS 357 { 358 BYTE Prob[4]; 359 } INTEL_HOSTVLD_VP9_PARTITION_PROBS, *PINTEL_HOSTVLD_VP9_PARTITION_PROBS; 360 361 // BAC engine definitions 362 typedef DWORD INTEL_HOSTVLD_VP9_BAC_VALUE; 363 364 typedef struct _INTEL_HOSTVLD_VP9_BAC_ENGINE 365 { 366 PBYTE pBuf; 367 PBYTE pBufEnd; 368 INTEL_HOSTVLD_VP9_BAC_VALUE BacValue; 369 INT iCount; 370 UINT uiRange; 371 } INTEL_HOSTVLD_VP9_BAC_ENGINE, *PINTEL_HOSTVLD_VP9_BAC_ENGINE; 372 373 typedef struct _INTEL_HOSTVLD_VP9_TKN_TREE_NODE 374 { 375 union 376 { 377 INT8 i8Token; 378 INT8 i8Offset; 379 }; 380 UINT8 ui8Prob; 381 } INTEL_HOSTVLD_VP9_TKN_TREE_NODE, *PINTEL_HOSTVLD_VP9_TKN_TREE_NODE, *INTEL_HOSTVLD_VP9_TKN_TREE; 382 383 typedef INTEL_HOSTVLD_VP9_TKN_TREE_NODE INTEL_HOSTVLD_VP9_INTRA_MODE_TREE[VP9_TKN_TREE_SZ(INTRA_MODE_COUNT)]; 384 typedef INTEL_HOSTVLD_VP9_TKN_TREE_NODE INTEL_HOSTVLD_VP9_SEGMENT_TREE[VP9_TKN_TREE_SZ(VP9_MAX_SEGMENTS)]; 385 typedef INTEL_HOSTVLD_VP9_TKN_TREE_NODE INTEL_HOSTVLD_VP9_PARTITION_TREE[VP9_TKN_TREE_SZ(PARTITION_TYPES)]; 386 typedef struct _INTEL_HOSTVLD_VP9_STATE INTEL_HOSTVLD_VP9_STATE, *PINTEL_HOSTVLD_VP9_STATE; 387 typedef struct _INTEL_HOSTVLD_VP9_FRAME_STATE INTEL_HOSTVLD_VP9_FRAME_STATE, *PINTEL_HOSTVLD_VP9_FRAME_STATE; 388 typedef struct _INTEL_HOSTVLD_VP9_TILE_STATE INTEL_HOSTVLD_VP9_TILE_STATE, *PINTEL_HOSTVLD_VP9_TILE_STATE; 389 390 typedef union _INTEL_HOSTVLD_VP9_MV 391 { 392 struct 393 { 394 INT16 i16X; 395 INT16 i16Y; 396 }; 397 DWORD dwValue; 398 } INTEL_HOSTVLD_VP9_MV, *PINTEL_HOSTVLD_VP9_MV; 399 400 // Segmentation feature 401 typedef struct _INTEL_HOSTVLD_VP9_SEG_FEATURE 402 { 403 INT16 Data[SEG_LVL_MAX]; 404 UINT uiMask; 405 } INTEL_HOSTVLD_VP9_SEG_FEATURE, *PINTEL_HOSTVLD_VP9_SEG_FEATURE; 406 407 typedef struct _INTEL_HOSTVLD_VP9_MV_PROB_SET 408 { 409 UINT8 MvSignProbs; 410 UINT8 MvClassProbs[VP9_MV_CLASSES - 1]; 411 UINT8 MvClass0Probs[VP9_MV_CLASS0_SIZE - 1]; 412 UINT8 MvBitsProbs[VP9_MV_OFFSET_BITS]; 413 UINT8 MvClass0FpProbs[VP9_MV_CLASS0_SIZE][4 - 1]; 414 UINT8 MvFpProbs[4 - 1]; 415 UINT8 MvClass0HpProbs; 416 UINT8 MvHpProbs; 417 } INTEL_HOSTVLD_VP9_MV_PROB_SET, *PINTEL_HOSTVLD_VP9_MV_PROB_SET; 418 419 typedef struct _INTEL_HOSTVLD_VP9_MV_COUNT_SET 420 { 421 UINT MvSignCounts[2]; 422 UINT MvClassCounts[VP9_MV_CLASSES]; 423 UINT MvClass0Counts[VP9_MV_CLASS0_SIZE]; 424 UINT MvBitsCounts[VP9_MV_OFFSET_BITS][2]; 425 UINT MvClass0FpCounts[VP9_MV_CLASS0_SIZE][4]; 426 UINT MvFpCounts[4]; 427 UINT MvClass0HpCounts[2]; 428 UINT MvHpCounts[2]; 429 } INTEL_HOSTVLD_VP9_MV_COUNT_SET, *PINTEL_HOSTVLD_VP9_MV_COUNT_SET; 430 431 typedef struct _INTEL_HOSTVLD_VP9_TX_PROB_TABLE_SET 432 { 433 UINT8 Tx_32X32[VP9_TX_SIZE_CONTEXTS][TX_32X32]; 434 UINT8 Tx_16X16[VP9_TX_SIZE_CONTEXTS][TX_16X16]; 435 UINT8 Tx_8X8[VP9_TX_SIZE_CONTEXTS][TX_8X8]; 436 } INTEL_HOSTVLD_VP9_TX_PROB_TABLE_SET, *PINTEL_HOSTVLD_VP9_TX_PROB_TABLE_SET; 437 438 typedef struct _INTEL_HOSTVLD_VP9_TX_COUNT_TABLE_SET 439 { 440 UINT Tx_32X32[VP9_TX_SIZE_CONTEXTS][TX_32X32 + 1]; 441 UINT Tx_16X16[VP9_TX_SIZE_CONTEXTS][TX_16X16 + 1]; 442 UINT Tx_8X8[VP9_TX_SIZE_CONTEXTS][TX_8X8 + 1]; 443 } INTEL_HOSTVLD_VP9_TX_COUNT_TABLE_SET, *PINTEL_HOSTVLD_VP9_TX_COUNT_TABLE_SET; 444 445 typedef struct _INTEL_HOSTVLD_VP9_TX_PROB_TABLE 446 { 447 PUINT8 pui8ProbTable; 448 UINT uiStride; 449 } INTEL_HOSTVLD_VP9_TX_PROB_TABLE; 450 typedef struct _INTEL_HOSTVLD_VP9_TX_COUNT_TABLE 451 { 452 PUINT puiCountTable; 453 UINT uiStride; 454 } INTEL_HOSTVLD_VP9_TX_COUNT_TABLE; 455 456 typedef UINT8 INTEL_HOSTVLD_VP9_COEFF_PROBS_MODEL[REF_TYPES][VP9_COEF_BANDS] 457 [VP9_PREV_COEF_CONTEXTS] 458 [VP9_UNCONSTRAINED_NODES]; 459 460 typedef UINT INTEL_HOSTVLD_VP9_COEFF_COUNT_MODEL[REF_TYPES][VP9_COEF_BANDS] 461 [VP9_PREV_COEF_CONTEXTS] 462 [VP9_UNCONSTRAINED_NODES + 1]; 463 typedef UINT INTEL_HOSTVLD_VP9_EOB_BRANCH_COUNT_MODEL[REF_TYPES][VP9_COEF_BANDS][VP9_PREV_COEF_CONTEXTS]; 464 465 typedef struct _INTEL_HOSTVLD_VP9_COUNT 466 { 467 INTEL_HOSTVLD_VP9_COEFF_COUNT_MODEL CoeffCounts[TX_SIZES][INTEL_HOSTVLD_VP9_YUV_PLANE_NUMBER]; 468 INTEL_HOSTVLD_VP9_EOB_BRANCH_COUNT_MODEL EobBranchCounts[TX_SIZES][INTEL_HOSTVLD_VP9_YUV_PLANE_NUMBER]; 469 INTEL_HOSTVLD_VP9_TX_COUNT_TABLE_SET TxCountSet; 470 471 UINT IntraModeCounts_Y[VP9_BLK_SIZE_GROUPS][INTRA_MODE_COUNT]; 472 UINT IntraModeCounts_UV[INTRA_MODE_COUNT][INTRA_MODE_COUNT]; 473 UINT MbSkipCounts[VP9_MBSKIP_CONTEXTS][2]; 474 UINT PartitionCounts[VP9_PARTITION_CONTEXTS][PARTITION_TYPES]; 475 UINT InterModeCounts[VP9_INTER_MODE_CONTEXTS][INTER_MODE_COUNT]; 476 UINT SwitchableInterpCounts[VP9_SWITCHABLE_FILTER_CONTEXTS][VP9_SWITCHABLE_FILTERS]; 477 UINT IntraInterCounts[VP9_INTRA_INTER_CONTEXTS][2]; 478 UINT CompoundInterCounts[VP9_COMPOUND_INTER_CONTEXTS][2]; 479 UINT SingleRefCounts[VP9_REF_CONTEXTS][2][2]; 480 UINT CompoundRefCounts[VP9_REF_CONTEXTS][2]; 481 482 UINT MvJointCounts[VP9_MV_JOINTS]; 483 INTEL_HOSTVLD_VP9_MV_COUNT_SET MvCountSet[VP9_MV_COMPONENTS]; 484 } INTEL_HOSTVLD_VP9_COUNT, *PINTEL_HOSTVLD_VP9_COUNT; 485 486 typedef struct _INTEL_HOSTVLD_VP9_FRAME_CONTEXT 487 { 488 INTEL_HOSTVLD_VP9_INTRA_MODE_TREE ModeTree_Y[VP9_BLK_SIZE_GROUPS]; 489 INTEL_HOSTVLD_VP9_INTRA_MODE_TREE ModeTree_UV[INTRA_MODE_COUNT]; 490 INTEL_HOSTVLD_VP9_SEGMENT_TREE SegmentTree; 491 INTEL_HOSTVLD_VP9_PARTITION_PROBS PartitionProbs[VP9_PARTITION_CONTEXTS]; 492 493 INTEL_HOSTVLD_VP9_TX_PROB_TABLE_SET TxProbTableSet; 494 INTEL_HOSTVLD_VP9_TX_PROB_TABLE TxProbTables[TX_SIZES]; //{NULL, table_set.Tx_8X8, table_set.Tx_16X16, table_set.Tx_32X32} 495 UINT8 MbSkipProbs[VP9_MBSKIP_CONTEXTS]; 496 INTEL_HOSTVLD_VP9_COEFF_PROBS_MODEL CoeffProbs[TX_SIZES][INTEL_HOSTVLD_VP9_YUV_PLANE_NUMBER]; 497 498 // context for inter 499 UINT8 SegPredProbs[VP9_SEG_PRED_PROBS]; 500 UINT8 InterModeProbs[VP9_INTER_MODE_CONTEXTS][INTER_MODE_COUNT - 1]; 501 UINT8 SwitchableInterpProbs[VP9_SWITCHABLE_FILTER_CONTEXTS][VP9_SWITCHABLE_FILTERS - 1]; 502 UINT8 IntraInterProbs[VP9_INTRA_INTER_CONTEXTS]; 503 UINT8 CompoundInterProbs[VP9_COMPOUND_INTER_CONTEXTS]; 504 UINT8 SingleRefProbs[VP9_REF_CONTEXTS][2]; 505 UINT8 CompoundRefProbs[VP9_REF_CONTEXTS]; 506 // mv context 507 UINT8 MvJointProbs[VP9_MV_JOINTS - 1]; 508 INTEL_HOSTVLD_VP9_MV_PROB_SET MvProbSet[VP9_MV_COMPONENTS]; 509 510 } INTEL_HOSTVLD_VP9_FRAME_CONTEXT, *PINTEL_HOSTVLD_VP9_FRAME_CONTEXT; 511 512 typedef struct _INTEL_HOSTVLD_VP9_CONTEXT 513 { 514 PINTEL_HOSTVLD_VP9_COUNT pCurrCount; 515 INTEL_HOSTVLD_VP9_FRAME_CONTEXT CurrContext; 516 INTEL_HOSTVLD_VP9_FRAME_CONTEXT ContextTable[4]; 517 } INTEL_HOSTVLD_VP9_CONTEXT, *PINTEL_HOSTVLD_VP9_CONTEXT; 518 519 typedef struct _INTEL_HOSTVLD_VP9_LOOP_FILTER_MASK 520 { 521 UINT64 LeftY[TX_SIZES]; 522 UINT64 AboveY[TX_SIZES]; 523 UINT64 Int4x4Y; 524 UINT16 LeftUv[TX_SIZES]; 525 UINT16 AboveUv[TX_SIZES]; 526 UINT16 Int4x4Uv; 527 } INTEL_HOSTVLD_VP9_LOOP_FILTER_MASK, *PINTEL_HOSTVLD_VP9_LOOP_FILTER_MASK; 528 529 typedef struct _INTEL_HOSTVLD_VP9_MODE_INFO 530 { 531 union 532 { 533 struct 534 { 535 UINT8 ui8BlockSize; 536 UINT8 ui8SegId; 537 UINT8 ui8TxSizeChroma; 538 UINT8 ui8PredModeChroma; 539 }; 540 struct 541 { 542 DWORD dwValue; 543 }; 544 } DW0; 545 546 union 547 { 548 struct 549 { 550 UINT8 ui8Flags; // bit 0: NOT skipped; bit 1: is inter 551 UINT8 ui8FilterLevel; // loop filter level 552 UINT8 ui8TxSizeLuma; 553 UINT8 ui8FilterType; 554 }; 555 struct 556 { 557 DWORD dwValue; 558 }; 559 } DW1; 560 561 // DW2 562 union 563 { 564 UINT8 PredModeLuma[2][2]; 565 DWORD dwPredModeLuma; 566 }; 567 568 // DW3 569 union 570 { 571 UINT8 TxTypeLuma[2][2]; 572 DWORD dwTxTypeLuma; 573 }; 574 } INTEL_HOSTVLD_VP9_MODE_INFO, *PINTEL_HOSTVLD_VP9_MODE_INFO; 575 576 typedef struct _INTEL_HOSTVLD_VP9_NEIGHBOR 577 { 578 union 579 { 580 struct 581 { 582 UINT8 ui8SkipFlag; 583 UINT8 ui8IsInter; 584 UINT8 ui8TxSizeLuma; 585 UINT8 ui8FilterType; 586 }; 587 struct 588 { 589 DWORD dwValue; 590 }; 591 } DW0; 592 593 union 594 { 595 struct 596 { 597 UINT8 ui8PartitionCtx; 598 UINT8 ui8SegPredFlag; 599 UINT8 ui8Reserved1; 600 UINT8 ui8Reserved2; 601 }; 602 struct 603 { 604 DWORD dwValue; 605 }; 606 } DW1; 607 } INTEL_HOSTVLD_VP9_NEIGHBOR, *PINTEL_HOSTVLD_VP9_NEIGHBOR; 608 609 typedef struct _INTEL_HOSTVLD_VP9_TILE_INFO 610 { 611 DWORD dwTileWidth; // tile width in 8x8 block 612 DWORD dwTileHeight; // tile height in 8x8 block 613 DWORD dwTileTop; // tile top index in 8x8 block 614 DWORD dwTileLeft; // tile left index in 8x8 block 615 INTEL_HOSTVLD_VP9_1D_BUFFER BitsBuffer; 616 } INTEL_HOSTVLD_VP9_TILE_INFO, *PINTEL_HOSTVLD_VP9_TILE_INFO; 617 618 // MB level info 619 typedef struct _INTEL_HOSTVLD_VP9_MB_INFO 620 { 621 // 8x8 token 622 PUINT8 pLastSegmentId; 623 PUINT16 pReferenceFrame; 624 PUINT16 pPrevRefFrame; 625 626 // 4x4 token 627 PINTEL_HOSTVLD_VP9_MV pMotionVector; // 2 MVs per 4x4 block 628 PINTEL_HOSTVLD_VP9_MV pPrevMv; // 2 MVs per 4x4 block 629 630 // context related 631 INTEL_HOSTVLD_VP9_NEIGHBOR ContextLeft[VP9_B64_SIZE_IN_B8]; // Left context; above context is defined in FRAME_INFO structure 632 PINTEL_HOSTVLD_VP9_NEIGHBOR pContextLeft; // Point to left context of current block 633 PINTEL_HOSTVLD_VP9_NEIGHBOR pContextAbove; // Point to above context of current block 634 // Entropy context for coeff decode 635 UINT8 EntropyContextLeft[VP9_CODED_YUV_PLANES][16]; 636 UINT8 TokenCache[VP9_TOKEN_CACHE_SIZE]; 637 638 // Mode info cache for 64x64 super block 639 PINTEL_HOSTVLD_VP9_MODE_INFO pModeInfoCache; 640 INT8 RefFrameIndexCache[VP9_B64_SIZE_IN_B8 * VP9_B64_SIZE_IN_B8 * 2]; 641 INTEL_HOSTVLD_VP9_MV MvCache[VP9_B64_SIZE_IN_B4 * VP9_B64_SIZE_IN_B4 * 2]; 642 643 PINTEL_HOSTVLD_VP9_MODE_INFO pMode; 644 PINTEL_HOSTVLD_VP9_MODE_INFO pModeLeft; 645 PINTEL_HOSTVLD_VP9_MODE_INFO pModeAbove; 646 PINT8 pRefFrameIndex; 647 PINTEL_HOSTVLD_VP9_MV pMv; 648 DWORD dwOffsetInB64; // offset of current block in 64x64 super block in scan order. in unit of 8x8 block. 649 650 PINTEL_HOSTVLD_VP9_TILE_INFO pCurrTile; 651 652 // 1D offset for current MB in zigzag order in unit of 8x8 block 653 DWORD dwMbOffset; 654 655 // distance between the head of the current line and 656 // the end of the last line in 8x8 token buffer 657 DWORD dwLineDist; 658 659 // MB position in unit of 8x8 block 660 DWORD dwMbPosX; 661 DWORD dwMbPosY; 662 663 // MB position in 64x64, 8x8 granularity 664 INT iMbPosInB64X; 665 INT iMbPosInB64Y; 666 667 INT iB4Number; 668 INT iLCtxOffset; 669 INT iACtxOffset; 670 INT8 i8ZOrder; 671 INT8 i8SegReference; 672 UINT8 ui8PartitionCtxLeft; 673 UINT8 ui8PartitionCtxAbove; 674 BOOL bAboveValid; 675 BOOL bLeftValid; 676 BOOL bSegRefSkip; 677 BOOL bSegRefEnabled; 678 679 INTEL_HOSTVLD_VP9_MV BestMv[2]; 680 INTEL_HOSTVLD_VP9_MV NearestMv[2]; 681 INTEL_HOSTVLD_VP9_MV NearMv[2]; 682 683 // Entropy context for Above and Left 684 PUINT8 pAboveContext[VP9_CODED_YUV_PLANES]; // TOCHECK: when and how to initialize these entropy contexts? 685 PUINT8 pLeftContext[VP9_CODED_YUV_PLANES]; 686 687 // Loop filter 688 INTEL_HOSTVLD_VP9_LOOP_FILTER_MASK LoopFilterMaskSB; 689 PDWORD pdwBlockSize; 690 PDWORD pdwTxSizeLuma; 691 PDWORD pdwTxSizeChroma; 692 PDWORD pdwFilterType; 693 PDWORD pdwPredModeChroma; 694 PDWORD pdwQPLuma; 695 PDWORD pdwQPChroma; 696 PDWORD pdwPredModeLuma; 697 PDWORD pdwTxTypeLuma; 698 } INTEL_HOSTVLD_VP9_MB_INFO, *PINTEL_HOSTVLD_VP9_MB_INFO; 699 700 // Frame level info 701 typedef struct _INTEL_HOSTVLD_VP9_FRAME_INFO 702 { 703 // Currently only support subsampling_x=subsampling_y=1 for Chroma plane 704 // INT iChromaPlaneSubSamplingX; 705 // INT iChromaPlaneSubSamplingY; 706 707 PINTEL_VP9_PIC_PARAMS pPicParams; 708 709 // Segmentation data 710 PINTEL_VP9_SEGMENT_PARAMS pSegmentData; 711 UINT8 ui8SegEnabled; 712 UINT8 ui8SegUpdMap; 713 UINT8 ui8TemporalUpd; 714 715 DWORD dwPicWidth; 716 DWORD dwPicHeight; 717 DWORD dwPicWidthCropped; 718 DWORD dwPicHeightCropped; 719 DWORD dwPicWidthAligned; 720 DWORD dwLog2TileRows; 721 DWORD dwLog2TileColumns; 722 DWORD dwTileRows; 723 DWORD dwTileColumns; 724 DWORD dwB8Rows; 725 DWORD dwB8RowsAligned; 726 DWORD dwB8Columns; 727 DWORD dwB8ColumnsAligned; 728 BOOL bIsKeyFrame; 729 730 // Partition 731 INTEL_HOSTVLD_VP9_1D_BUFFER FirstPartition; 732 INTEL_HOSTVLD_VP9_1D_BUFFER SecondPartition; 733 734 DWORD dwMbStride; 735 BOOL bLossLess; 736 BOOL bIsIntraOnly; 737 BOOL bFrameParallelDisabled; 738 BOOL bErrorResilientMode; 739 BOOL bShowFrame; 740 BOOL bResetContext; 741 UINT uiFrameContextIndex; 742 UINT uiResetFrameContext; 743 UINT32 SegQP[INTEL_HOSTVLD_VP9_YUV_PLANE_NUMBER][VP9_MAX_SEGMENTS]; 744 745 INTEL_HOSTVLD_VP9_TX_MODE TxMode; 746 INTEL_HOSTVLD_VP9_FRAME_TYPE LastFrameType; 747 748 PINTEL_HOSTVLD_VP9_FRAME_CONTEXT pContext; 749 INTEL_HOSTVLD_VP9_TILE_INFO TileInfo[VP9_MAX_TILES]; 750 751 INTEL_HOSTVLD_VP9_1D_BUFFER ModeInfo; 752 753 // Above context related 754 DWORD dwNumAboveCtx; // Number of elements for above context in 8x8 blocks 755 PINTEL_HOSTVLD_VP9_NEIGHBOR pContextAbove; // Above context; left context is defined in MB_INFO structure 756 INTEL_HOSTVLD_VP9_1D_BUFFER EntropyContextAbove; 757 PUINT8 pEntropyContextAbove[VP9_CODED_YUV_PLANES]; // Entropy context for coeff decode 758 759 // Inter 760 BOOL bIsSwitchableInterpolation; 761 BOOL bAllowHighPrecisionMv; 762 BOOL RefFrameSignBias[VP9_REF_FRAME_MAX]; 763 BOOL bHasPrevFrame; 764 DWORD dwPredictionMode; 765 INTEL_HOSTVLD_VP9_REF_FRAME CompondFixedRef; 766 INTEL_HOSTVLD_VP9_REF_FRAME CompondVarRef[2]; 767 INTEL_HOSTVLD_VP9_INTERPOLATION_TYPE eInterpolationType; 768 769 VAStatus (* pfnParseFrmModeInfo) ( 770 PINTEL_HOSTVLD_VP9_TILE_STATE pTileState); 771 } INTEL_HOSTVLD_VP9_FRAME_INFO, *PINTEL_HOSTVLD_VP9_FRAME_INFO; 772 773 774 // Multi-threading 775 typedef struct _INTEL_HOSTVLD_VP9_MULTI_THREAD 776 { 777 BOOL bTileParallel; 778 BOOL bFrameParallel; 779 BOOL bParserMDParallel; 780 781 DWORD dwParserThreadNumber; 782 783 // Thread handles 784 HANDLE* phParserThread; 785 HANDLE hMDThread; 786 787 // Thread sync 788 HANDLE* phParserThreadStart; 789 HANDLE* phParserThreadFinish; 790 HANDLE phMDThreadStart; 791 HANDLE phMDThreadFinish; 792 } INTEL_HOSTVLD_VP9_MULTI_THREAD, *PINTEL_HOSTVLD_VP9_MULTI_THREAD; 793 794 typedef struct _INTEL_HOSTVLD_VP9_TASK_USERDATA 795 { 796 PINTEL_HOSTVLD_VP9_VIDEO_BUFFER pVideoBuffer; 797 PINTEL_HOSTVLD_VP9_OUTPUT_BUFFER pOutputBuffer; 798 799 DWORD dwCurrIndex; 800 DWORD dwPrevIndex; 801 802 INTEL_HOSTVLD_VP9_FRAME_TYPE LastFrameType; 803 PINTEL_HOSTVLD_VP9_FRAME_CONTEXT pCurrContext; 804 PINTEL_HOSTVLD_VP9_1D_BUFFER pLastSegIdBuf; 805 } INTEL_HOSTVLD_VP9_TASK_USERDATA, *PINTEL_HOSTVLD_VP9_TASK_USERDATA; 806 807 struct _INTEL_HOSTVLD_VP9_TILE_STATE 808 { 809 PINTEL_HOSTVLD_VP9_FRAME_STATE pFrameState; 810 INTEL_HOSTVLD_VP9_BAC_ENGINE BacEngine; 811 INTEL_HOSTVLD_VP9_MB_INFO MbInfo; 812 INTEL_HOSTVLD_VP9_COUNT Count; 813 DWORD dwCurrColIndex; 814 }; 815 816 struct _INTEL_HOSTVLD_VP9_FRAME_STATE 817 { 818 PINTEL_HOSTVLD_VP9_STATE pVp9HostVld; 819 PINTEL_HOSTVLD_VP9_VIDEO_BUFFER pVideoBuffer; 820 PINTEL_HOSTVLD_VP9_OUTPUT_BUFFER pOutputBuffer; 821 INTEL_HOSTVLD_VP9_BAC_ENGINE BacEngine; 822 INTEL_HOSTVLD_VP9_FRAME_INFO FrameInfo; 823 INTEL_HOSTVLD_VP9_1D_BUFFER ReferenceFrame; // Y, U and V share the same reference frame buffer 824 PINTEL_HOSTVLD_VP9_1D_BUFFER pLastSegIdBuf; // For inter frame seg id prediction. 825 struct object_surface *pRenderTarget; 826 827 PINTEL_HOSTVLD_VP9_TILE_STATE pTileStateBase; 828 DWORD dwTileStatesInUse; 829 830 DWORD dwCurrIndex; 831 DWORD dwPrevIndex; 832 833 DWORD dwLastTaskID; 834 INTEL_HOSTVLD_VP9_FRAME_TYPE LastFrameType; 835 }; 836 837 typedef struct _INTEL_HOSTVLD_VP9_EARLY_DEC_BUFFER 838 { 839 INTEL_HOSTVLD_VP9_1D_BUFFER LastSegId; 840 INTEL_HOSTVLD_VP9_FRAME_CONTEXT CurrContext; 841 }INTEL_HOSTVLD_VP9_EARLY_DEC_BUFFER, *PINTEL_HOSTVLD_VP9_EARLY_DEC_BUFFER; 842 843 // Hostvld state 844 struct _INTEL_HOSTVLD_VP9_STATE 845 { 846 847 PINTEL_HOSTVLD_VP9_FRAME_STATE pFrameStateBase; 848 PINTEL_HOSTVLD_VP9_VIDEO_BUFFER pVideoBufferBase; 849 PINTEL_HOSTVLD_VP9_OUTPUT_BUFFER pOutputBufferBase; 850 PINTEL_HOSTVLD_VP9_TASK_USERDATA pTaskUserData; 851 DWORD dwThreadNumber; 852 DWORD dwBufferNumber; 853 854 DWORD dwDDIBufNumber; 855 DWORD dwCurrDDIBufIndex; 856 DWORD dwPrevDDIBufIndex; 857 INTEL_HOSTVLD_VP9_FRAME_CONTEXT ContextTable[4]; 858 859 INTEL_HOSTVLD_VP9_FRAME_TYPE LastFrameType; 860 DWORD dwCurrIndex; 861 DWORD dwTaskUserDataIndex; 862 863 PFNINTEL_HOSTVLD_VP9_RENDERCB pfnRenderCb; 864 PFNINTEL_HOSTVLD_VP9_SYNCCB pfnSyncCb; 865 866 UINT uiTileParserID[VP9_MAX_TILE_COLUMNS]; 867 UINT PrevParserID; 868 UINT PrevLPID; 869 UINT PrevMDFID; 870 871 MOS_SEMAPHORE SemAllTaskDone; 872 MOS_MUTEX MutexSync; 873 DWORD dwPendingTaskNum; 874 BOOL bIsDestroyCall; 875 PMOS_SEMAPHORE *ppEnqueueSem; 876 PMOS_SEMAPHORE *ppUnrefedSem; 877 PMOS_MUTEX *ppResourceMutex; 878 PMOS_MUTEX pMutexRefCount; 879 880 PINTEL_HOSTVLD_VP9_EARLY_DEC_BUFFER pEarlyDecBufferBase; //memory base for buffers used for early decoding 881 UINT8 ui8BufNumEarlyDec; //number of buffer set for early decoding 882 PUINT pLastParserTaskID; //parser task id of the last frame using same early dec buffer 883 UINT8 ui8BufIdxEarlyDec; //buffer index to pEarlyDecBufferBase 884 885 PVOID pvStandardState; 886 887 }; 888 889 #endif // __INTEL_HOSTVLD_VP9_INTERNAL_H__ 890