| /dports/sysutils/edk2/edk2-platforms-89f6170d/Platform/Intel/WhiskeylakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/ |
| H A D | TbtSmm.c | 60 STATIC UINT8 TbtSegment = 0; variable
98 DeviceBase = PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Bus, Device, Function, 0); in PcieFindExtendedCapId()
391 CapHeaderOffset = PcieFindCapId (TbtSegment, Bus, Dev, Fun, 0x10); in MultiFunctionDeviceAspm()
411 CapHeaderOffset = PcieFindCapId (TbtSegment, Bus, Dev, Fun, 0x10); in MultiFunctionDeviceAspm()
583 CapHeaderOffset_B = PcieFindCapId (TbtSegment, SecBus, 0, 0, 0x10); in DownstreamAspmSupport()
616 CapHeaderOffset_B = PcieFindCapId (TbtSegment, SecBus, 0, 0, 0x10); in RootportAspmSupport()
658 TbtSegment = (UINT8)RpSegment; in ThunderboltEnableAspmWithoutLtr()
848 TbtSegment = (UINT8)RpSegment; in ThunderboltDisableAspmWithoutLtr()
979 TbtSegment = (UINT8)RpSegment; in ConfigureTbtPm()
1080 TbtSegment = (UINT8)RpSegment; in ConfigureLtr()
[all …]
|
| H A D | TbtSmiHandler.c | 29 STATIC UINT8 TbtSegment = 0; variable
50 gDeviceBaseAddress = PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Bus, Dev, Fun, 0); in UnsetVesc()
74 gDeviceBaseAddress = PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Dbus, 0x00, 0x00, 0); in UnsetVesc()
77 gDeviceBaseAddress = PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Bus, Dev, Fun, 0); in UnsetVesc()
158 gDeviceBaseAddress = PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Bus, Dev, 0x00, 0); in SetPhyPortResources()
351 gDeviceBaseAddress = PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Bus, Dev, Fun, 0); in SetDevResources()
821 TbtSegment = (UINT8)RpSegment; in InitializeHostRouter()
974 gDeviceBaseAddress = PCI_SEGMENT_LIB_ADDRESS (TbtSegment,Bus, Dev, 0x00, 0); in SetCioPortResources()
1399 gDeviceBaseAddress = PCI_SEGMENT_LIB_ADDRESS (TbtSegment,Bus, Dev, Fun, 0); in GetPortResources()
1425 gDeviceBaseAddress = PCI_SEGMENT_LIB_ADDRESS (TbtSegment,Bus, Dev, Fun, 0); in ConfigurePort()
[all …]
|
| /dports/sysutils/edk2/edk2-platforms-89f6170d/Platform/Intel/CometlakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/ |
| H A D | TbtSmm.c | 60 STATIC UINT8 TbtSegment = 0; variable
98 DeviceBase = PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Bus, Device, Function, 0); in PcieFindExtendedCapId()
391 CapHeaderOffset = PcieFindCapId (TbtSegment, Bus, Dev, Fun, 0x10); in MultiFunctionDeviceAspm()
411 CapHeaderOffset = PcieFindCapId (TbtSegment, Bus, Dev, Fun, 0x10); in MultiFunctionDeviceAspm()
583 CapHeaderOffset_B = PcieFindCapId (TbtSegment, SecBus, 0, 0, 0x10); in DownstreamAspmSupport()
616 CapHeaderOffset_B = PcieFindCapId (TbtSegment, SecBus, 0, 0, 0x10); in RootportAspmSupport()
658 TbtSegment = (UINT8)RpSegment; in ThunderboltEnableAspmWithoutLtr()
848 TbtSegment = (UINT8)RpSegment; in ThunderboltDisableAspmWithoutLtr()
979 TbtSegment = (UINT8)RpSegment; in ConfigureTbtPm()
1080 TbtSegment = (UINT8)RpSegment; in ConfigureLtr()
[all …]
|
| H A D | TbtSmiHandler.c | 29 STATIC UINT8 TbtSegment = 0; variable
50 gDeviceBaseAddress = PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Bus, Dev, Fun, 0); in UnsetVesc()
74 gDeviceBaseAddress = PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Dbus, 0x00, 0x00, 0); in UnsetVesc()
77 gDeviceBaseAddress = PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Bus, Dev, Fun, 0); in UnsetVesc()
158 gDeviceBaseAddress = PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Bus, Dev, 0x00, 0); in SetPhyPortResources()
351 gDeviceBaseAddress = PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Bus, Dev, Fun, 0); in SetDevResources()
821 TbtSegment = (UINT8)RpSegment; in InitializeHostRouter()
974 gDeviceBaseAddress = PCI_SEGMENT_LIB_ADDRESS (TbtSegment,Bus, Dev, 0x00, 0); in SetCioPortResources()
1399 gDeviceBaseAddress = PCI_SEGMENT_LIB_ADDRESS (TbtSegment,Bus, Dev, Fun, 0); in GetPortResources()
1425 gDeviceBaseAddress = PCI_SEGMENT_LIB_ADDRESS (TbtSegment,Bus, Dev, Fun, 0); in ConfigurePort()
[all …]
|
| /dports/sysutils/edk2/edk2-platforms-89f6170d/Platform/Intel/KabylakeOpenBoardPkg/Features/Tbt/TbtInit/Smm/ |
| H A D | TbtSmm.c | 61 STATIC UINT8 TbtSegment = 0; variable
99 DeviceBase = PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Bus, Device, Function, 0); in PcieFindExtendedCapId()
392 CapHeaderOffset = PcieFindCapId (TbtSegment, Bus, Dev, Fun, 0x10); in MultiFunctionDeviceAspm()
412 CapHeaderOffset = PcieFindCapId (TbtSegment, Bus, Dev, Fun, 0x10); in MultiFunctionDeviceAspm()
584 CapHeaderOffset_B = PcieFindCapId (TbtSegment, SecBus, 0, 0, 0x10); in DownstreamAspmSupport()
617 CapHeaderOffset_B = PcieFindCapId (TbtSegment, SecBus, 0, 0, 0x10); in RootportAspmSupport()
659 TbtSegment = (UINT8)RpSegment; in ThunderboltEnableAspmWithoutLtr()
849 TbtSegment = (UINT8)RpSegment; in ThunderboltDisableAspmWithoutLtr()
980 TbtSegment = (UINT8)RpSegment; in ConfigureTbtPm()
1081 TbtSegment = (UINT8)RpSegment; in ConfigureLtr()
[all …]
|
| H A D | TbtSmiHandler.c | 30 STATIC UINT8 TbtSegment = 0; variable
51 gDeviceBaseAddress = PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Bus, Dev, Fun, 0); in UnsetVesc()
75 gDeviceBaseAddress = PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Dbus, 0x00, 0x00, 0); in UnsetVesc()
78 gDeviceBaseAddress = PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Bus, Dev, Fun, 0); in UnsetVesc()
159 gDeviceBaseAddress = PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Bus, Dev, 0x00, 0); in SetPhyPortResources()
352 gDeviceBaseAddress = PCI_SEGMENT_LIB_ADDRESS (TbtSegment, Bus, Dev, Fun, 0); in SetDevResources()
822 TbtSegment = (UINT8)RpSegment; in InitializeHostRouter()
975 gDeviceBaseAddress = PCI_SEGMENT_LIB_ADDRESS (TbtSegment,Bus, Dev, 0x00, 0); in SetCioPortResources()
1400 gDeviceBaseAddress = PCI_SEGMENT_LIB_ADDRESS (TbtSegment,Bus, Dev, Fun, 0); in GetPortResources()
1426 gDeviceBaseAddress = PCI_SEGMENT_LIB_ADDRESS (TbtSegment,Bus, Dev, Fun, 0); in ConfigurePort()
[all …]
|