| /dports/sysutils/edk2/edk2-platforms-89f6170d/Platform/Intel/MinPlatformPkg/Test/Library/TestPointCheckLib/ |
| H A D | SmmCheckPaging.c | 256 UINTN TileDataSize; in IsSmmSaveState() local
263 TileDataSize = (SMRAM_SAVE_STATE_MAP_OFFSET - TXT_SMM_PSD_OFFSET) + sizeof (SMRAM_SAVE_STATE_MAP); in IsSmmSaveState()
264 TileDataSize = ALIGN_VALUE(TileDataSize, SIZE_4KB); in IsSmmSaveState()
265 TileSize = TileDataSize + TileCodeSize - 1; in IsSmmSaveState()
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| /dports/emulators/qemu60/qemu-6.0.0/roms/edk2/UefiCpuPkg/PiSmmCpuDxeSmm/ |
| H A D | PiSmmCpuDxeSmm.c | 547 UINTN TileDataSize; in PiCpuSmmEntry() local
763 TileDataSize = (SMRAM_SAVE_STATE_MAP_OFFSET - SMM_PSD_OFFSET) + sizeof (SMRAM_SAVE_STATE_MAP); in PiCpuSmmEntry()
764 TileDataSize = ALIGN_VALUE(TileDataSize, SIZE_4KB); in PiCpuSmmEntry()
765 TileSize = TileDataSize + TileCodeSize - 1; in PiCpuSmmEntry()
767 …((EFI_D_INFO, "SMRAM TileSize = 0x%08x (0x%08x, 0x%08x)\n", TileSize, TileCodeSize, TileDataSize)); in PiCpuSmmEntry()
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| H A D | SmmCpuMemoryManagement.c | 805 UINTN TileDataSize; in PatchSmmSaveStateMap() local
810 TileDataSize = (SMRAM_SAVE_STATE_MAP_OFFSET - SMM_PSD_OFFSET) + sizeof (SMRAM_SAVE_STATE_MAP); in PatchSmmSaveStateMap()
811 TileDataSize = ALIGN_VALUE(TileDataSize, SIZE_4KB); in PatchSmmSaveStateMap()
812 TileSize = TileDataSize + TileCodeSize - 1; in PatchSmmSaveStateMap()
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| /dports/emulators/qemu42/qemu-4.2.1/roms/edk2/UefiCpuPkg/PiSmmCpuDxeSmm/ |
| H A D | PiSmmCpuDxeSmm.c | 545 UINTN TileDataSize; in PiCpuSmmEntry() local
761 TileDataSize = (SMRAM_SAVE_STATE_MAP_OFFSET - SMM_PSD_OFFSET) + sizeof (SMRAM_SAVE_STATE_MAP); in PiCpuSmmEntry()
762 TileDataSize = ALIGN_VALUE(TileDataSize, SIZE_4KB); in PiCpuSmmEntry()
763 TileSize = TileDataSize + TileCodeSize - 1; in PiCpuSmmEntry()
765 …((EFI_D_INFO, "SMRAM TileSize = 0x%08x (0x%08x, 0x%08x)\n", TileSize, TileCodeSize, TileDataSize)); in PiCpuSmmEntry()
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| H A D | SmmCpuMemoryManagement.c | 787 UINTN TileDataSize; in PatchSmmSaveStateMap() local
792 TileDataSize = (SMRAM_SAVE_STATE_MAP_OFFSET - SMM_PSD_OFFSET) + sizeof (SMRAM_SAVE_STATE_MAP); in PatchSmmSaveStateMap()
793 TileDataSize = ALIGN_VALUE(TileDataSize, SIZE_4KB); in PatchSmmSaveStateMap()
794 TileSize = TileDataSize + TileCodeSize - 1; in PatchSmmSaveStateMap()
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| /dports/emulators/qemu/qemu-6.2.0/roms/edk2/UefiCpuPkg/PiSmmCpuDxeSmm/ |
| H A D | PiSmmCpuDxeSmm.c | 547 UINTN TileDataSize; in PiCpuSmmEntry() local
763 TileDataSize = (SMRAM_SAVE_STATE_MAP_OFFSET - SMM_PSD_OFFSET) + sizeof (SMRAM_SAVE_STATE_MAP); in PiCpuSmmEntry()
764 TileDataSize = ALIGN_VALUE(TileDataSize, SIZE_4KB); in PiCpuSmmEntry()
765 TileSize = TileDataSize + TileCodeSize - 1; in PiCpuSmmEntry()
767 …((EFI_D_INFO, "SMRAM TileSize = 0x%08x (0x%08x, 0x%08x)\n", TileSize, TileCodeSize, TileDataSize)); in PiCpuSmmEntry()
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| H A D | SmmCpuMemoryManagement.c | 805 UINTN TileDataSize; in PatchSmmSaveStateMap() local
810 TileDataSize = (SMRAM_SAVE_STATE_MAP_OFFSET - SMM_PSD_OFFSET) + sizeof (SMRAM_SAVE_STATE_MAP); in PatchSmmSaveStateMap()
811 TileDataSize = ALIGN_VALUE(TileDataSize, SIZE_4KB); in PatchSmmSaveStateMap()
812 TileSize = TileDataSize + TileCodeSize - 1; in PatchSmmSaveStateMap()
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| /dports/emulators/qemu-utils/qemu-4.2.1/roms/edk2/UefiCpuPkg/PiSmmCpuDxeSmm/ |
| H A D | PiSmmCpuDxeSmm.c | 545 UINTN TileDataSize; in PiCpuSmmEntry() local
761 TileDataSize = (SMRAM_SAVE_STATE_MAP_OFFSET - SMM_PSD_OFFSET) + sizeof (SMRAM_SAVE_STATE_MAP); in PiCpuSmmEntry()
762 TileDataSize = ALIGN_VALUE(TileDataSize, SIZE_4KB); in PiCpuSmmEntry()
763 TileSize = TileDataSize + TileCodeSize - 1; in PiCpuSmmEntry()
765 …((EFI_D_INFO, "SMRAM TileSize = 0x%08x (0x%08x, 0x%08x)\n", TileSize, TileCodeSize, TileDataSize)); in PiCpuSmmEntry()
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| H A D | SmmCpuMemoryManagement.c | 787 UINTN TileDataSize; in PatchSmmSaveStateMap() local
792 TileDataSize = (SMRAM_SAVE_STATE_MAP_OFFSET - SMM_PSD_OFFSET) + sizeof (SMRAM_SAVE_STATE_MAP); in PatchSmmSaveStateMap()
793 TileDataSize = ALIGN_VALUE(TileDataSize, SIZE_4KB); in PatchSmmSaveStateMap()
794 TileSize = TileDataSize + TileCodeSize - 1; in PatchSmmSaveStateMap()
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| /dports/emulators/qemu5/qemu-5.2.0/roms/edk2/UefiCpuPkg/PiSmmCpuDxeSmm/ |
| H A D | PiSmmCpuDxeSmm.c | 547 UINTN TileDataSize; in PiCpuSmmEntry() local
763 TileDataSize = (SMRAM_SAVE_STATE_MAP_OFFSET - SMM_PSD_OFFSET) + sizeof (SMRAM_SAVE_STATE_MAP); in PiCpuSmmEntry()
764 TileDataSize = ALIGN_VALUE(TileDataSize, SIZE_4KB); in PiCpuSmmEntry()
765 TileSize = TileDataSize + TileCodeSize - 1; in PiCpuSmmEntry()
767 …((EFI_D_INFO, "SMRAM TileSize = 0x%08x (0x%08x, 0x%08x)\n", TileSize, TileCodeSize, TileDataSize)); in PiCpuSmmEntry()
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| H A D | SmmCpuMemoryManagement.c | 805 UINTN TileDataSize; in PatchSmmSaveStateMap() local
810 TileDataSize = (SMRAM_SAVE_STATE_MAP_OFFSET - SMM_PSD_OFFSET) + sizeof (SMRAM_SAVE_STATE_MAP); in PatchSmmSaveStateMap()
811 TileDataSize = ALIGN_VALUE(TileDataSize, SIZE_4KB); in PatchSmmSaveStateMap()
812 TileSize = TileDataSize + TileCodeSize - 1; in PatchSmmSaveStateMap()
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| /dports/sysutils/uefi-edk2-bhyve/edk2-edk2-stable202102/UefiCpuPkg/PiSmmCpuDxeSmm/ |
| H A D | PiSmmCpuDxeSmm.c | 547 UINTN TileDataSize; in PiCpuSmmEntry() local
763 TileDataSize = (SMRAM_SAVE_STATE_MAP_OFFSET - SMM_PSD_OFFSET) + sizeof (SMRAM_SAVE_STATE_MAP); in PiCpuSmmEntry()
764 TileDataSize = ALIGN_VALUE(TileDataSize, SIZE_4KB); in PiCpuSmmEntry()
765 TileSize = TileDataSize + TileCodeSize - 1; in PiCpuSmmEntry()
767 …((EFI_D_INFO, "SMRAM TileSize = 0x%08x (0x%08x, 0x%08x)\n", TileSize, TileCodeSize, TileDataSize)); in PiCpuSmmEntry()
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| H A D | SmmCpuMemoryManagement.c | 788 UINTN TileDataSize; in PatchSmmSaveStateMap() local
793 TileDataSize = (SMRAM_SAVE_STATE_MAP_OFFSET - SMM_PSD_OFFSET) + sizeof (SMRAM_SAVE_STATE_MAP); in PatchSmmSaveStateMap()
794 TileDataSize = ALIGN_VALUE(TileDataSize, SIZE_4KB); in PatchSmmSaveStateMap()
795 TileSize = TileDataSize + TileCodeSize - 1; in PatchSmmSaveStateMap()
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| /dports/sysutils/uefi-edk2-qemu/edk2-edk2-stable201911/UefiCpuPkg/PiSmmCpuDxeSmm/ |
| H A D | PiSmmCpuDxeSmm.c | 547 UINTN TileDataSize; in PiCpuSmmEntry() local
763 TileDataSize = (SMRAM_SAVE_STATE_MAP_OFFSET - SMM_PSD_OFFSET) + sizeof (SMRAM_SAVE_STATE_MAP); in PiCpuSmmEntry()
764 TileDataSize = ALIGN_VALUE(TileDataSize, SIZE_4KB); in PiCpuSmmEntry()
765 TileSize = TileDataSize + TileCodeSize - 1; in PiCpuSmmEntry()
767 …((EFI_D_INFO, "SMRAM TileSize = 0x%08x (0x%08x, 0x%08x)\n", TileSize, TileCodeSize, TileDataSize)); in PiCpuSmmEntry()
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| H A D | SmmCpuMemoryManagement.c | 805 UINTN TileDataSize; in PatchSmmSaveStateMap() local
810 TileDataSize = (SMRAM_SAVE_STATE_MAP_OFFSET - SMM_PSD_OFFSET) + sizeof (SMRAM_SAVE_STATE_MAP); in PatchSmmSaveStateMap()
811 TileDataSize = ALIGN_VALUE(TileDataSize, SIZE_4KB); in PatchSmmSaveStateMap()
812 TileSize = TileDataSize + TileCodeSize - 1; in PatchSmmSaveStateMap()
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| /dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/edk2/UefiCpuPkg/PiSmmCpuDxeSmm/ |
| H A D | PiSmmCpuDxeSmm.c | 545 UINTN TileDataSize; in PiCpuSmmEntry() local
761 TileDataSize = (SMRAM_SAVE_STATE_MAP_OFFSET - SMM_PSD_OFFSET) + sizeof (SMRAM_SAVE_STATE_MAP); in PiCpuSmmEntry()
762 TileDataSize = ALIGN_VALUE(TileDataSize, SIZE_4KB); in PiCpuSmmEntry()
763 TileSize = TileDataSize + TileCodeSize - 1; in PiCpuSmmEntry()
765 …((EFI_D_INFO, "SMRAM TileSize = 0x%08x (0x%08x, 0x%08x)\n", TileSize, TileCodeSize, TileDataSize)); in PiCpuSmmEntry()
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| H A D | SmmCpuMemoryManagement.c | 787 UINTN TileDataSize; in PatchSmmSaveStateMap() local
792 TileDataSize = (SMRAM_SAVE_STATE_MAP_OFFSET - SMM_PSD_OFFSET) + sizeof (SMRAM_SAVE_STATE_MAP); in PatchSmmSaveStateMap()
793 TileDataSize = ALIGN_VALUE(TileDataSize, SIZE_4KB); in PatchSmmSaveStateMap()
794 TileSize = TileDataSize + TileCodeSize - 1; in PatchSmmSaveStateMap()
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| /dports/sysutils/edk2/edk2-edk2-stable202102/UefiCpuPkg/PiSmmCpuDxeSmm/ |
| H A D | PiSmmCpuDxeSmm.c | 547 UINTN TileDataSize;
763 TileDataSize = (SMRAM_SAVE_STATE_MAP_OFFSET - SMM_PSD_OFFSET) + sizeof (SMRAM_SAVE_STATE_MAP);
764 TileDataSize = ALIGN_VALUE(TileDataSize, SIZE_4KB);
765 TileSize = TileDataSize + TileCodeSize - 1;
767 …((EFI_D_INFO, "SMRAM TileSize = 0x%08x (0x%08x, 0x%08x)\n", TileSize, TileCodeSize, TileDataSize));
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| H A D | SmmCpuMemoryManagement.c | 788 UINTN TileDataSize; in PatchSmmSaveStateMap() local
793 TileDataSize = (SMRAM_SAVE_STATE_MAP_OFFSET - SMM_PSD_OFFSET) + sizeof (SMRAM_SAVE_STATE_MAP); in PatchSmmSaveStateMap()
794 TileDataSize = ALIGN_VALUE(TileDataSize, SIZE_4KB); in PatchSmmSaveStateMap()
795 TileSize = TileDataSize + TileCodeSize - 1; in PatchSmmSaveStateMap()
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