Home
last modified time | relevance | path

Searched refs:Tln (Results 1 – 25 of 163) sorted by relevance

1234567

/dports/multimedia/v4l-utils/linux-5.13-rc2/arch/arm/mach-pxa/include/mach/
H A Dregs-lcd.h105 #define LCCR2_VrtSnchWdth(Tln) (((Tln) - 1) << FShft (LCCR2_VSW)) argument
108 #define LCCR2_EndFrmDel(Tln) ((Tln) << FShft (LCCR2_EFW)) argument
111 #define LCCR2_BegFrmDel(Tln) ((Tln) << FShft (LCCR2_BFW)) argument
/dports/multimedia/v4l_compat/linux-5.13-rc2/arch/arm/mach-pxa/include/mach/
H A Dregs-lcd.h105 #define LCCR2_VrtSnchWdth(Tln) (((Tln) - 1) << FShft (LCCR2_VSW)) argument
108 #define LCCR2_EndFrmDel(Tln) ((Tln) << FShft (LCCR2_EFW)) argument
111 #define LCCR2_BegFrmDel(Tln) ((Tln) << FShft (LCCR2_BFW)) argument
/dports/multimedia/libv4l/linux-5.13-rc2/arch/arm/mach-pxa/include/mach/
H A Dregs-lcd.h105 #define LCCR2_VrtSnchWdth(Tln) (((Tln) - 1) << FShft (LCCR2_VSW)) argument
108 #define LCCR2_EndFrmDel(Tln) ((Tln) << FShft (LCCR2_EFW)) argument
111 #define LCCR2_BegFrmDel(Tln) ((Tln) << FShft (LCCR2_BFW)) argument
/dports/multimedia/v4l-utils/linux-5.13-rc2/arch/arm/mach-sa1100/include/mach/
H A DSA-1100.h1736 #define LCCR2_VrtSnchWdth(Tln) /* Vertical Synchronization pulse */ \ argument
1738 (((Tln) - 1) << FShft (LCCR2_VSW))
1741 #define LCCR2_EndFrmDel(Tln) /* End-of-Frame Delay */ \ argument
1743 ((Tln) << FShft (LCCR2_EFW))
1746 #define LCCR2_BegFrmDel(Tln) /* Beginning-of-Frame Delay */ \ argument
1748 ((Tln) << FShft (LCCR2_BFW))
/dports/multimedia/v4l_compat/linux-5.13-rc2/arch/arm/mach-sa1100/include/mach/
H A DSA-1100.h1736 #define LCCR2_VrtSnchWdth(Tln) /* Vertical Synchronization pulse */ \ argument
1738 (((Tln) - 1) << FShft (LCCR2_VSW))
1741 #define LCCR2_EndFrmDel(Tln) /* End-of-Frame Delay */ \ argument
1743 ((Tln) << FShft (LCCR2_EFW))
1746 #define LCCR2_BegFrmDel(Tln) /* Beginning-of-Frame Delay */ \ argument
1748 ((Tln) << FShft (LCCR2_BFW))
/dports/multimedia/libv4l/linux-5.13-rc2/arch/arm/mach-sa1100/include/mach/
H A DSA-1100.h1736 #define LCCR2_VrtSnchWdth(Tln) /* Vertical Synchronization pulse */ \ argument
1738 (((Tln) - 1) << FShft (LCCR2_VSW))
1741 #define LCCR2_EndFrmDel(Tln) /* End-of-Frame Delay */ \ argument
1743 ((Tln) << FShft (LCCR2_EFW))
1746 #define LCCR2_BegFrmDel(Tln) /* Beginning-of-Frame Delay */ \ argument
1748 ((Tln) << FShft (LCCR2_BFW))
/dports/emulators/qemu42/qemu-4.2.1/roms/u-boot/arch/arm/include/asm/arch-pxa/
H A Dpxa-regs.h2162 #define LCCR2_VrtSnchWdth(Tln) /* Vertical Synchronization pulse */ \ argument
2164 (((Tln) - 1) << FShft (LCCR2_VSW))
2168 #define LCCR2_EndFrmDel(Tln) /* End-of-Frame Delay */ \ argument
2170 ((Tln) << FShft (LCCR2_EFW))
2174 #define LCCR2_BegFrmDel(Tln) /* Beginning-of-Frame Delay */ \ argument
2176 ((Tln) << FShft (LCCR2_BFW))
/dports/emulators/qemu/qemu-6.2.0/roms/u-boot/arch/arm/include/asm/arch-pxa/
H A Dpxa-regs.h2162 #define LCCR2_VrtSnchWdth(Tln) /* Vertical Synchronization pulse */ \ argument
2164 (((Tln) - 1) << FShft (LCCR2_VSW))
2168 #define LCCR2_EndFrmDel(Tln) /* End-of-Frame Delay */ \ argument
2170 ((Tln) << FShft (LCCR2_EFW))
2174 #define LCCR2_BegFrmDel(Tln) /* Beginning-of-Frame Delay */ \ argument
2176 ((Tln) << FShft (LCCR2_BFW))
/dports/emulators/qemu5/qemu-5.2.0/roms/u-boot/arch/arm/include/asm/arch-pxa/
H A Dpxa-regs.h2162 #define LCCR2_VrtSnchWdth(Tln) /* Vertical Synchronization pulse */ \ argument
2164 (((Tln) - 1) << FShft (LCCR2_VSW))
2168 #define LCCR2_EndFrmDel(Tln) /* End-of-Frame Delay */ \ argument
2170 ((Tln) << FShft (LCCR2_EFW))
2174 #define LCCR2_BegFrmDel(Tln) /* Beginning-of-Frame Delay */ \ argument
2176 ((Tln) << FShft (LCCR2_BFW))
/dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/arch/arm/include/asm/arch-pxa/
H A Dpxa-regs.h2162 #define LCCR2_VrtSnchWdth(Tln) /* Vertical Synchronization pulse */ \ argument
2164 (((Tln) - 1) << FShft (LCCR2_VSW))
2168 #define LCCR2_EndFrmDel(Tln) /* End-of-Frame Delay */ \ argument
2170 ((Tln) << FShft (LCCR2_EFW))
2174 #define LCCR2_BegFrmDel(Tln) /* Beginning-of-Frame Delay */ \ argument
2176 ((Tln) << FShft (LCCR2_BFW))
/dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/arch/arm/include/asm/arch-pxa/
H A Dpxa-regs.h2162 #define LCCR2_VrtSnchWdth(Tln) /* Vertical Synchronization pulse */ \ argument
2164 (((Tln) - 1) << FShft (LCCR2_VSW))
2168 #define LCCR2_EndFrmDel(Tln) /* End-of-Frame Delay */ \ argument
2170 ((Tln) << FShft (LCCR2_EFW))
2174 #define LCCR2_BegFrmDel(Tln) /* Beginning-of-Frame Delay */ \ argument
2176 ((Tln) << FShft (LCCR2_BFW))
/dports/sysutils/u-boot-olinuxino-lime2-emmc/u-boot-2021.07/arch/arm/include/asm/arch-pxa/
H A Dpxa-regs.h2162 #define LCCR2_VrtSnchWdth(Tln) /* Vertical Synchronization pulse */ \ argument
2164 (((Tln) - 1) << FShft (LCCR2_VSW))
2168 #define LCCR2_EndFrmDel(Tln) /* End-of-Frame Delay */ \ argument
2170 ((Tln) << FShft (LCCR2_EFW))
2174 #define LCCR2_BegFrmDel(Tln) /* Beginning-of-Frame Delay */ \ argument
2176 ((Tln) << FShft (LCCR2_BFW))
/dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/arch/arm/include/asm/arch-pxa/
H A Dpxa-regs.h2162 #define LCCR2_VrtSnchWdth(Tln) /* Vertical Synchronization pulse */ \ argument
2164 (((Tln) - 1) << FShft (LCCR2_VSW))
2168 #define LCCR2_EndFrmDel(Tln) /* End-of-Frame Delay */ \ argument
2170 ((Tln) << FShft (LCCR2_EFW))
2174 #define LCCR2_BegFrmDel(Tln) /* Beginning-of-Frame Delay */ \ argument
2176 ((Tln) << FShft (LCCR2_BFW))
/dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/arch/arm/include/asm/arch-pxa/
H A Dpxa-regs.h2162 #define LCCR2_VrtSnchWdth(Tln) /* Vertical Synchronization pulse */ \ argument
2164 (((Tln) - 1) << FShft (LCCR2_VSW))
2168 #define LCCR2_EndFrmDel(Tln) /* End-of-Frame Delay */ \ argument
2170 ((Tln) << FShft (LCCR2_EFW))
2174 #define LCCR2_BegFrmDel(Tln) /* Beginning-of-Frame Delay */ \ argument
2176 ((Tln) << FShft (LCCR2_BFW))
/dports/sysutils/u-boot-firefly-rk3399/u-boot-2021.07/arch/arm/include/asm/arch-pxa/
H A Dpxa-regs.h2162 #define LCCR2_VrtSnchWdth(Tln) /* Vertical Synchronization pulse */ \ argument
2164 (((Tln) - 1) << FShft (LCCR2_VSW))
2168 #define LCCR2_EndFrmDel(Tln) /* End-of-Frame Delay */ \ argument
2170 ((Tln) << FShft (LCCR2_EFW))
2174 #define LCCR2_BegFrmDel(Tln) /* Beginning-of-Frame Delay */ \ argument
2176 ((Tln) << FShft (LCCR2_BFW))
/dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/arch/arm/include/asm/arch-pxa/
H A Dpxa-regs.h2162 #define LCCR2_VrtSnchWdth(Tln) /* Vertical Synchronization pulse */ \ argument
2164 (((Tln) - 1) << FShft (LCCR2_VSW))
2168 #define LCCR2_EndFrmDel(Tln) /* End-of-Frame Delay */ \ argument
2170 ((Tln) << FShft (LCCR2_EFW))
2174 #define LCCR2_BegFrmDel(Tln) /* Beginning-of-Frame Delay */ \ argument
2176 ((Tln) << FShft (LCCR2_BFW))
/dports/sysutils/u-boot-sopine/u-boot-2021.07/arch/arm/include/asm/arch-pxa/
H A Dpxa-regs.h2162 #define LCCR2_VrtSnchWdth(Tln) /* Vertical Synchronization pulse */ \ argument
2164 (((Tln) - 1) << FShft (LCCR2_VSW))
2168 #define LCCR2_EndFrmDel(Tln) /* End-of-Frame Delay */ \ argument
2170 ((Tln) << FShft (LCCR2_EFW))
2174 #define LCCR2_BegFrmDel(Tln) /* Beginning-of-Frame Delay */ \ argument
2176 ((Tln) << FShft (LCCR2_BFW))
/dports/sysutils/u-boot-bananapi/u-boot-2021.07/arch/arm/include/asm/arch-pxa/
H A Dpxa-regs.h2162 #define LCCR2_VrtSnchWdth(Tln) /* Vertical Synchronization pulse */ \ argument
2164 (((Tln) - 1) << FShft (LCCR2_VSW))
2168 #define LCCR2_EndFrmDel(Tln) /* End-of-Frame Delay */ \ argument
2170 ((Tln) << FShft (LCCR2_EFW))
2174 #define LCCR2_BegFrmDel(Tln) /* Beginning-of-Frame Delay */ \ argument
2176 ((Tln) << FShft (LCCR2_BFW))
/dports/sysutils/u-boot-sopine-spi/u-boot-2021.07/arch/arm/include/asm/arch-pxa/
H A Dpxa-regs.h2162 #define LCCR2_VrtSnchWdth(Tln) /* Vertical Synchronization pulse */ \ argument
2164 (((Tln) - 1) << FShft (LCCR2_VSW))
2168 #define LCCR2_EndFrmDel(Tln) /* End-of-Frame Delay */ \ argument
2170 ((Tln) << FShft (LCCR2_EFW))
2174 #define LCCR2_BegFrmDel(Tln) /* Beginning-of-Frame Delay */ \ argument
2176 ((Tln) << FShft (LCCR2_BFW))
/dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/arch/arm/include/asm/arch-pxa/
H A Dpxa-regs.h2162 #define LCCR2_VrtSnchWdth(Tln) /* Vertical Synchronization pulse */ \ argument
2164 (((Tln) - 1) << FShft (LCCR2_VSW))
2168 #define LCCR2_EndFrmDel(Tln) /* End-of-Frame Delay */ \ argument
2170 ((Tln) << FShft (LCCR2_EFW))
2174 #define LCCR2_BegFrmDel(Tln) /* Beginning-of-Frame Delay */ \ argument
2176 ((Tln) << FShft (LCCR2_BFW))
/dports/sysutils/u-boot-rpi-0-w/u-boot-2021.07/arch/arm/include/asm/arch-pxa/
H A Dpxa-regs.h2162 #define LCCR2_VrtSnchWdth(Tln) /* Vertical Synchronization pulse */ \ argument
2164 (((Tln) - 1) << FShft (LCCR2_VSW))
2168 #define LCCR2_EndFrmDel(Tln) /* End-of-Frame Delay */ \ argument
2170 ((Tln) << FShft (LCCR2_EFW))
2174 #define LCCR2_BegFrmDel(Tln) /* Beginning-of-Frame Delay */ \ argument
2176 ((Tln) << FShft (LCCR2_BFW))
/dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/arch/arm/include/asm/arch-pxa/
H A Dpxa-regs.h2162 #define LCCR2_VrtSnchWdth(Tln) /* Vertical Synchronization pulse */ \ argument
2164 (((Tln) - 1) << FShft (LCCR2_VSW))
2168 #define LCCR2_EndFrmDel(Tln) /* End-of-Frame Delay */ \ argument
2170 ((Tln) << FShft (LCCR2_EFW))
2174 #define LCCR2_BegFrmDel(Tln) /* Beginning-of-Frame Delay */ \ argument
2176 ((Tln) << FShft (LCCR2_BFW))
/dports/sysutils/u-boot-nanopi-neo/u-boot-2021.07/arch/arm/include/asm/arch-pxa/
H A Dpxa-regs.h2162 #define LCCR2_VrtSnchWdth(Tln) /* Vertical Synchronization pulse */ \ argument
2164 (((Tln) - 1) << FShft (LCCR2_VSW))
2168 #define LCCR2_EndFrmDel(Tln) /* End-of-Frame Delay */ \ argument
2170 ((Tln) << FShft (LCCR2_EFW))
2174 #define LCCR2_BegFrmDel(Tln) /* Beginning-of-Frame Delay */ \ argument
2176 ((Tln) << FShft (LCCR2_BFW))
/dports/sysutils/u-boot-nanopi-a64/u-boot-2021.07/arch/arm/include/asm/arch-pxa/
H A Dpxa-regs.h2162 #define LCCR2_VrtSnchWdth(Tln) /* Vertical Synchronization pulse */ \ argument
2164 (((Tln) - 1) << FShft (LCCR2_VSW))
2168 #define LCCR2_EndFrmDel(Tln) /* End-of-Frame Delay */ \ argument
2170 ((Tln) << FShft (LCCR2_EFW))
2174 #define LCCR2_BegFrmDel(Tln) /* Beginning-of-Frame Delay */ \ argument
2176 ((Tln) << FShft (LCCR2_BFW))
/dports/sysutils/u-boot-nanopi-neo-air/u-boot-2021.07/arch/arm/include/asm/arch-pxa/
H A Dpxa-regs.h2162 #define LCCR2_VrtSnchWdth(Tln) /* Vertical Synchronization pulse */ \ argument
2164 (((Tln) - 1) << FShft (LCCR2_VSW))
2168 #define LCCR2_EndFrmDel(Tln) /* End-of-Frame Delay */ \ argument
2170 ((Tln) << FShft (LCCR2_EFW))
2174 #define LCCR2_BegFrmDel(Tln) /* Beginning-of-Frame Delay */ \ argument
2176 ((Tln) << FShft (LCCR2_BFW))

1234567