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Searched refs:U4_16 (Results 1 – 25 of 25) sorted by relevance

/dports/devel/gdb761/gdb-7.6.1/opcodes/
H A Ds390-opc.c191 #define U4_16 56 /* 4 bit unsigned value starting at 16 */ macro
351 #define INSTR_RRF_U0FF 4, { F_24,U4_16,F_28,0,0,0 } /* e.g. fixr */
352 #define INSTR_RRF_U0FEFE 4, { FE_24,U4_16,FE_28,0,0,0 } /* e.g. fixbr */
353 #define INSTR_RRF_U0RF 4, { R_24,U4_16,F_28,0,0,0 } /* e.g. cfebr */
354 #define INSTR_RRF_U0RFE 4, { R_24,U4_16,FE_28,0,0,0 } /* e.g. cfxbr */
355 #define INSTR_RRF_UUFF 4, { F_24,U4_16,F_28,U4_20,0,0 } /* e.g. fidtr */
356 #define INSTR_RRF_UUFFE 4, { F_24,U4_16,FE_28,U4_20,0,0 } /* e.g. ldxtr */
357 #define INSTR_RRF_UUFEFE 4, { FE_24,U4_16,FE_28,U4_20,0,0 } /* e.g. fixtr */
365 #define INSTR_RRF_U0RR 4, { R_24,R_28,U4_16,0,0,0 } /* e.g. clrt */
367 #define INSTR_RRF_UUFR 4, { F_24,U4_16,R_28,U4_20,0,0 } /* e.g. cdgtra */
[all …]
/dports/lang/gnatdroid-binutils-x86/binutils-2.27/opcodes/
H A Ds390-opc.c197 #define U4_16 57 /* 4 bit unsigned value starting at 16 */ macro
360 #define INSTR_RRF_U0FF 4, { F_24,U4_16,F_28,0,0,0 } /* e.g. fidbr */
361 #define INSTR_RRF_U0FEFE 4, { FE_24,U4_16,FE_28,0,0,0 } /* e.g. fixbr */
362 #define INSTR_RRF_U0RF 4, { R_24,U4_16,F_28,0,0,0 } /* e.g. cfebr */
363 #define INSTR_RRF_U0RFE 4, { R_24,U4_16,FE_28,0,0,0 } /* e.g. cfxbr */
364 #define INSTR_RRF_UUFF 4, { F_24,U4_16,F_28,U4_20,0,0 } /* e.g. fidtr */
365 #define INSTR_RRF_UUFFE 4, { F_24,U4_16,FE_28,U4_20,0,0 } /* e.g. ldxtr */
366 #define INSTR_RRF_UUFEFE 4, { FE_24,U4_16,FE_28,U4_20,0,0 } /* e.g. fixtr */
371 #define INSTR_RRF_U0RR 4, { R_24,R_28,U4_16,0,0,0 } /* e.g. sske */
372 #define INSTR_RRF_U0RER 4, { RE_24,R_28,U4_16,0,0,0 } /* e.g. trte */
[all …]
/dports/lang/gnatdroid-binutils/binutils-2.27/opcodes/
H A Ds390-opc.c197 #define U4_16 57 /* 4 bit unsigned value starting at 16 */ macro
360 #define INSTR_RRF_U0FF 4, { F_24,U4_16,F_28,0,0,0 } /* e.g. fidbr */
361 #define INSTR_RRF_U0FEFE 4, { FE_24,U4_16,FE_28,0,0,0 } /* e.g. fixbr */
362 #define INSTR_RRF_U0RF 4, { R_24,U4_16,F_28,0,0,0 } /* e.g. cfebr */
363 #define INSTR_RRF_U0RFE 4, { R_24,U4_16,FE_28,0,0,0 } /* e.g. cfxbr */
364 #define INSTR_RRF_UUFF 4, { F_24,U4_16,F_28,U4_20,0,0 } /* e.g. fidtr */
365 #define INSTR_RRF_UUFFE 4, { F_24,U4_16,FE_28,U4_20,0,0 } /* e.g. ldxtr */
366 #define INSTR_RRF_UUFEFE 4, { FE_24,U4_16,FE_28,U4_20,0,0 } /* e.g. fixtr */
371 #define INSTR_RRF_U0RR 4, { R_24,R_28,U4_16,0,0,0 } /* e.g. sske */
372 #define INSTR_RRF_U0RER 4, { RE_24,R_28,U4_16,0,0,0 } /* e.g. trte */
[all …]
/dports/devel/arm-elf-binutils/binutils-2.37/opcodes/
H A Ds390-opc.c197 #define U4_16 57 /* 4 bit unsigned value starting at 16 */ macro
366 #define INSTR_RRF_U0FF 4, { F_24,U4_16,F_28,0,0,0 } /* e.g. fidbr */
367 #define INSTR_RRF_U0FEFE 4, { FE_24,U4_16,FE_28,0,0,0 } /* e.g. fixbr */
368 #define INSTR_RRF_U0RF 4, { R_24,U4_16,F_28,0,0,0 } /* e.g. cfebr */
369 #define INSTR_RRF_U0RFE 4, { R_24,U4_16,FE_28,0,0,0 } /* e.g. cfxbr */
370 #define INSTR_RRF_UUFF 4, { F_24,U4_16,F_28,U4_20,0,0 } /* e.g. fidtr */
371 #define INSTR_RRF_UUFFE 4, { F_24,U4_16,FE_28,U4_20,0,0 } /* e.g. ldxtr */
372 #define INSTR_RRF_UUFEFE 4, { FE_24,U4_16,FE_28,U4_20,0,0 } /* e.g. fixtr */
377 #define INSTR_RRF_U0RR 4, { R_24,R_28,U4_16,0,0,0 } /* e.g. sske */
378 #define INSTR_RRF_U0RER 4, { RE_24,R_28,U4_16,0,0,0 } /* e.g. trte */
[all …]
/dports/devel/gdb/gdb-11.1/opcodes/
H A Ds390-opc.c197 #define U4_16 57 /* 4 bit unsigned value starting at 16 */ macro
366 #define INSTR_RRF_U0FF 4, { F_24,U4_16,F_28,0,0,0 } /* e.g. fidbr */
367 #define INSTR_RRF_U0FEFE 4, { FE_24,U4_16,FE_28,0,0,0 } /* e.g. fixbr */
368 #define INSTR_RRF_U0RF 4, { R_24,U4_16,F_28,0,0,0 } /* e.g. cfebr */
369 #define INSTR_RRF_U0RFE 4, { R_24,U4_16,FE_28,0,0,0 } /* e.g. cfxbr */
370 #define INSTR_RRF_UUFF 4, { F_24,U4_16,F_28,U4_20,0,0 } /* e.g. fidtr */
371 #define INSTR_RRF_UUFFE 4, { F_24,U4_16,FE_28,U4_20,0,0 } /* e.g. ldxtr */
372 #define INSTR_RRF_UUFEFE 4, { FE_24,U4_16,FE_28,U4_20,0,0 } /* e.g. fixtr */
377 #define INSTR_RRF_U0RR 4, { R_24,R_28,U4_16,0,0,0 } /* e.g. sske */
378 #define INSTR_RRF_U0RER 4, { RE_24,R_28,U4_16,0,0,0 } /* e.g. trte */
[all …]
/dports/devel/gnulibiberty/binutils-2.37/opcodes/
H A Ds390-opc.c197 #define U4_16 57 /* 4 bit unsigned value starting at 16 */ macro
366 #define INSTR_RRF_U0FF 4, { F_24,U4_16,F_28,0,0,0 } /* e.g. fidbr */
367 #define INSTR_RRF_U0FEFE 4, { FE_24,U4_16,FE_28,0,0,0 } /* e.g. fixbr */
368 #define INSTR_RRF_U0RF 4, { R_24,U4_16,F_28,0,0,0 } /* e.g. cfebr */
369 #define INSTR_RRF_U0RFE 4, { R_24,U4_16,FE_28,0,0,0 } /* e.g. cfxbr */
370 #define INSTR_RRF_UUFF 4, { F_24,U4_16,F_28,U4_20,0,0 } /* e.g. fidtr */
371 #define INSTR_RRF_UUFFE 4, { F_24,U4_16,FE_28,U4_20,0,0 } /* e.g. ldxtr */
372 #define INSTR_RRF_UUFEFE 4, { FE_24,U4_16,FE_28,U4_20,0,0 } /* e.g. fixtr */
377 #define INSTR_RRF_U0RR 4, { R_24,R_28,U4_16,0,0,0 } /* e.g. sske */
378 #define INSTR_RRF_U0RER 4, { RE_24,R_28,U4_16,0,0,0 } /* e.g. trte */
[all …]
/dports/devel/binutils/binutils-2.37/opcodes/
H A Ds390-opc.c197 #define U4_16 57 /* 4 bit unsigned value starting at 16 */ macro
366 #define INSTR_RRF_U0FF 4, { F_24,U4_16,F_28,0,0,0 } /* e.g. fidbr */
367 #define INSTR_RRF_U0FEFE 4, { FE_24,U4_16,FE_28,0,0,0 } /* e.g. fixbr */
368 #define INSTR_RRF_U0RF 4, { R_24,U4_16,F_28,0,0,0 } /* e.g. cfebr */
369 #define INSTR_RRF_U0RFE 4, { R_24,U4_16,FE_28,0,0,0 } /* e.g. cfxbr */
370 #define INSTR_RRF_UUFF 4, { F_24,U4_16,F_28,U4_20,0,0 } /* e.g. fidtr */
371 #define INSTR_RRF_UUFFE 4, { F_24,U4_16,FE_28,U4_20,0,0 } /* e.g. ldxtr */
372 #define INSTR_RRF_UUFEFE 4, { FE_24,U4_16,FE_28,U4_20,0,0 } /* e.g. fixtr */
377 #define INSTR_RRF_U0RR 4, { R_24,R_28,U4_16,0,0,0 } /* e.g. sske */
378 #define INSTR_RRF_U0RER 4, { RE_24,R_28,U4_16,0,0,0 } /* e.g. trte */
[all …]
/dports/devel/avr-gdb/gdb-7.3.1/opcodes/
H A Ds390-opc.c151 #define U4_16 40 /* 4 bit unsigned value starting at 16 */ macro
280 #define INSTR_RRF_U0FF 4, { F_24,U4_16,F_28,0,0,0 } /* e.g. fixr */
281 #define INSTR_RRF_U0RF 4, { R_24,U4_16,F_28,0,0,0 } /* e.g. cfebr */
282 #define INSTR_RRF_UUFF 4, { F_24,U4_16,F_28,U4_20,0,0 } /* e.g. fidtr */
286 #define INSTR_RRF_U0RR 4, { R_24,R_28,U4_16,0,0,0 } /* e.g. clrt */
288 #define INSTR_RRF_UUFR 4, { F_24,U4_16,R_28,U4_20,0,0 } /* e.g. cdgtra */
289 #define INSTR_RRF_UURF 4, { R_24,U4_16,F_28,U4_20,0,0 } /* e.g. cgdtra */
/dports/multimedia/v4l-utils/linux-5.13-rc2/arch/s390/kernel/
H A Ddis.c112 U4_16, /* 4 bit unsigned value starting at 16 */ enumerator
174 [U4_16] = { 4, 16, 0 },
242 [INSTR_RRF_U0FF] = { F_24, U4_16, F_28, 0, 0, 0 },
243 [INSTR_RRF_U0RF] = { R_24, U4_16, F_28, 0, 0, 0 },
244 [INSTR_RRF_U0RR] = { R_24, R_28, U4_16, 0, 0, 0 },
246 [INSTR_RRF_UUFF] = { F_24, U4_16, F_28, U4_20, 0, 0 },
247 [INSTR_RRF_UUFR] = { F_24, U4_16, R_28, U4_20, 0, 0 },
248 [INSTR_RRF_UURF] = { R_24, U4_16, F_28, U4_20, 0, 0 },
/dports/multimedia/v4l_compat/linux-5.13-rc2/arch/s390/kernel/
H A Ddis.c112 U4_16, /* 4 bit unsigned value starting at 16 */ enumerator
174 [U4_16] = { 4, 16, 0 },
242 [INSTR_RRF_U0FF] = { F_24, U4_16, F_28, 0, 0, 0 },
243 [INSTR_RRF_U0RF] = { R_24, U4_16, F_28, 0, 0, 0 },
244 [INSTR_RRF_U0RR] = { R_24, R_28, U4_16, 0, 0, 0 },
246 [INSTR_RRF_UUFF] = { F_24, U4_16, F_28, U4_20, 0, 0 },
247 [INSTR_RRF_UUFR] = { F_24, U4_16, R_28, U4_20, 0, 0 },
248 [INSTR_RRF_UURF] = { R_24, U4_16, F_28, U4_20, 0, 0 },
/dports/multimedia/libv4l/linux-5.13-rc2/arch/s390/kernel/
H A Ddis.c112 U4_16, /* 4 bit unsigned value starting at 16 */ enumerator
174 [U4_16] = { 4, 16, 0 },
242 [INSTR_RRF_U0FF] = { F_24, U4_16, F_28, 0, 0, 0 },
243 [INSTR_RRF_U0RF] = { R_24, U4_16, F_28, 0, 0, 0 },
244 [INSTR_RRF_U0RR] = { R_24, R_28, U4_16, 0, 0, 0 },
246 [INSTR_RRF_UUFF] = { F_24, U4_16, F_28, U4_20, 0, 0 },
247 [INSTR_RRF_UUFR] = { F_24, U4_16, R_28, U4_20, 0, 0 },
248 [INSTR_RRF_UURF] = { R_24, U4_16, F_28, U4_20, 0, 0 },
/dports/devel/tigcc/tigcc-0.96.b8_10/gnu/binutils-2.16.1/opcodes/
H A Ds390-opc.c115 #define U4_16 32 /* 4 bit unsigned value starting at 16 */ macro
200 #define INSTR_RRF_U0FF 4, { F_24,U4_16,F_28,0,0,0 } /* e.g. cfxbr */
201 #define INSTR_RRF_U0FR 4, { F_24,U4_16,R_28,0,0,0 } /* e.g. cfebr */
202 #define INSTR_RRF_U0FR 4, { F_24,U4_16,R_28,0,0,0 } /* e.g. cfxbr */
/dports/devel/zpu-gcc/zpu-toolchain-1.0/toolchain/binutils/opcodes/
H A Ds390-opc.c115 #define U4_16 32 /* 4 bit unsigned value starting at 16 */ macro
200 #define INSTR_RRF_U0FF 4, { F_24,U4_16,F_28,0,0,0 } /* e.g. cfxbr */
201 #define INSTR_RRF_U0FR 4, { F_24,U4_16,R_28,0,0,0 } /* e.g. cfebr */
202 #define INSTR_RRF_U0FR 4, { F_24,U4_16,R_28,0,0,0 } /* e.g. cfxbr */
/dports/devel/zpu-binutils/zpu-toolchain-1.0/toolchain/binutils/opcodes/
H A Ds390-opc.c115 #define U4_16 32 /* 4 bit unsigned value starting at 16 */ macro
200 #define INSTR_RRF_U0FF 4, { F_24,U4_16,F_28,0,0,0 } /* e.g. cfxbr */
201 #define INSTR_RRF_U0FR 4, { F_24,U4_16,R_28,0,0,0 } /* e.g. cfebr */
202 #define INSTR_RRF_U0FR 4, { F_24,U4_16,R_28,0,0,0 } /* e.g. cfxbr */
/dports/devel/djgpp-binutils/binutils-2.17/opcodes/
H A Ds390-opc.c115 #define U4_16 32 /* 4 bit unsigned value starting at 16 */ macro
209 #define INSTR_RRF_U0FF 4, { F_24,U4_16,F_28,0,0,0 } /* e.g. cfxbr */
210 #define INSTR_RRF_U0FR 4, { F_24,U4_16,R_28,0,0,0 } /* e.g. cfebr */
211 #define INSTR_RRF_U0FR 4, { F_24,U4_16,R_28,0,0,0 } /* e.g. cfxbr */
/dports/emulators/x49gp/x49gp/x49gp-code/qemu/qemu-git/
H A Ds390-dis.c505 #define U4_16 32 /* 4 bit unsigned value starting at 16 */ macro
608 #define INSTR_RRF_U0FF 4, { F_24,U4_16,F_28,0,0,0 } /* e.g. fixr */
609 #define INSTR_RRF_U0RF 4, { R_24,U4_16,F_28,0,0,0 } /* e.g. cfebr */
610 #define INSTR_RRF_UUFF 4, { F_24,U4_16,F_28,U4_20,0,0 } /* e.g. fidtr */
/dports/emulators/qemu/qemu-6.2.0/disas/
H A Ds390.c552 #define U4_16 32 /* 4 bit unsigned value starting at 16 */ macro
675 #define INSTR_RRF_U0FF 4, { F_24,U4_16,F_28,0,0,0 } /* e.g. fixr */
676 #define INSTR_RRF_U0RF 4, { R_24,U4_16,F_28,0,0,0 } /* e.g. cfebr */
677 #define INSTR_RRF_UUFF 4, { F_24,U4_16,F_28,U4_20,0,0 } /* e.g. fidtr */
/dports/emulators/qemu42/qemu-4.2.1/disas/
H A Ds390.c552 #define U4_16 32 /* 4 bit unsigned value starting at 16 */ macro
675 #define INSTR_RRF_U0FF 4, { F_24,U4_16,F_28,0,0,0 } /* e.g. fixr */
676 #define INSTR_RRF_U0RF 4, { R_24,U4_16,F_28,0,0,0 } /* e.g. cfebr */
677 #define INSTR_RRF_UUFF 4, { F_24,U4_16,F_28,U4_20,0,0 } /* e.g. fidtr */
/dports/emulators/qemu5/qemu-5.2.0/disas/
H A Ds390.c552 #define U4_16 32 /* 4 bit unsigned value starting at 16 */ macro
675 #define INSTR_RRF_U0FF 4, { F_24,U4_16,F_28,0,0,0 } /* e.g. fixr */
676 #define INSTR_RRF_U0RF 4, { R_24,U4_16,F_28,0,0,0 } /* e.g. cfebr */
677 #define INSTR_RRF_UUFF 4, { F_24,U4_16,F_28,U4_20,0,0 } /* e.g. fidtr */
/dports/emulators/qemu60/qemu-6.0.0/disas/
H A Ds390.c552 #define U4_16 32 /* 4 bit unsigned value starting at 16 */ macro
675 #define INSTR_RRF_U0FF 4, { F_24,U4_16,F_28,0,0,0 } /* e.g. fixr */
676 #define INSTR_RRF_U0RF 4, { R_24,U4_16,F_28,0,0,0 } /* e.g. cfebr */
677 #define INSTR_RRF_UUFF 4, { F_24,U4_16,F_28,U4_20,0,0 } /* e.g. fidtr */
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/disas/
H A Ds390.c553 #define U4_16 32 /* 4 bit unsigned value starting at 16 */ macro
676 #define INSTR_RRF_U0FF 4, { F_24,U4_16,F_28,0,0,0 } /* e.g. fixr */
677 #define INSTR_RRF_U0RF 4, { R_24,U4_16,F_28,0,0,0 } /* e.g. cfebr */
678 #define INSTR_RRF_UUFF 4, { F_24,U4_16,F_28,U4_20,0,0 } /* e.g. fidtr */
/dports/emulators/qemu-utils/qemu-4.2.1/disas/
H A Ds390.c552 #define U4_16 32 /* 4 bit unsigned value starting at 16 */ macro
675 #define INSTR_RRF_U0FF 4, { F_24,U4_16,F_28,0,0,0 } /* e.g. fixr */
676 #define INSTR_RRF_U0RF 4, { R_24,U4_16,F_28,0,0,0 } /* e.g. cfebr */
677 #define INSTR_RRF_UUFF 4, { F_24,U4_16,F_28,U4_20,0,0 } /* e.g. fidtr */
/dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/disas/
H A Ds390.c552 #define U4_16 32 /* 4 bit unsigned value starting at 16 */ macro
675 #define INSTR_RRF_U0FF 4, { F_24,U4_16,F_28,0,0,0 } /* e.g. fixr */
676 #define INSTR_RRF_U0RF 4, { R_24,U4_16,F_28,0,0,0 } /* e.g. cfebr */
677 #define INSTR_RRF_UUFF 4, { F_24,U4_16,F_28,U4_20,0,0 } /* e.g. fidtr */
/dports/emulators/qemu-guest-agent/qemu-5.0.1/disas/
H A Ds390.c552 #define U4_16 32 /* 4 bit unsigned value starting at 16 */ macro
675 #define INSTR_RRF_U0FF 4, { F_24,U4_16,F_28,0,0,0 } /* e.g. fixr */
676 #define INSTR_RRF_U0RF 4, { R_24,U4_16,F_28,0,0,0 } /* e.g. cfebr */
677 #define INSTR_RRF_UUFF 4, { F_24,U4_16,F_28,U4_20,0,0 } /* e.g. fidtr */
/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/disas/
H A Ds390.c552 #define U4_16 32 /* 4 bit unsigned value starting at 16 */ macro
675 #define INSTR_RRF_U0FF 4, { F_24,U4_16,F_28,0,0,0 } /* e.g. fixr */
676 #define INSTR_RRF_U0RF 4, { R_24,U4_16,F_28,0,0,0 } /* e.g. cfebr */
677 #define INSTR_RRF_UUFF 4, { F_24,U4_16,F_28,U4_20,0,0 } /* e.g. fidtr */