| /dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/arch/arm/mach-rockchip/px30/ |
| H A D | px30.c | 275 UART5_PLL_SEL_MASK | UART5_DIV_CON_MASK, in board_debug_uart_init()
|
| /dports/sysutils/u-boot-olinuxino-lime2-emmc/u-boot-2021.07/arch/arm/mach-rockchip/px30/ |
| H A D | px30.c | 275 UART5_PLL_SEL_MASK | UART5_DIV_CON_MASK, in board_debug_uart_init()
|
| /dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/arch/arm/mach-rockchip/px30/ |
| H A D | px30.c | 275 UART5_PLL_SEL_MASK | UART5_DIV_CON_MASK, in board_debug_uart_init()
|
| /dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/arch/arm/mach-rockchip/px30/ |
| H A D | px30.c | 275 UART5_PLL_SEL_MASK | UART5_DIV_CON_MASK, in board_debug_uart_init()
|
| /dports/sysutils/u-boot-firefly-rk3399/u-boot-2021.07/arch/arm/mach-rockchip/px30/ |
| H A D | px30.c | 275 UART5_PLL_SEL_MASK | UART5_DIV_CON_MASK, in board_debug_uart_init()
|
| /dports/sysutils/u-boot-sopine/u-boot-2021.07/arch/arm/mach-rockchip/px30/ |
| H A D | px30.c | 275 UART5_PLL_SEL_MASK | UART5_DIV_CON_MASK, in board_debug_uart_init()
|
| /dports/sysutils/u-boot-sinovoip-bpi-m3/u-boot-2021.07/arch/arm/mach-rockchip/px30/ |
| H A D | px30.c | 275 UART5_PLL_SEL_MASK | UART5_DIV_CON_MASK, in board_debug_uart_init()
|
| /dports/sysutils/u-boot-a13-olinuxino/u-boot-2021.07/arch/arm/mach-rockchip/px30/ |
| H A D | px30.c | 275 UART5_PLL_SEL_MASK | UART5_DIV_CON_MASK, in board_debug_uart_init()
|
| /dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/arch/arm/mach-rockchip/px30/ |
| H A D | px30.c | 275 UART5_PLL_SEL_MASK | UART5_DIV_CON_MASK, in board_debug_uart_init()
|
| /dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/arch/arm/mach-rockchip/px30/ |
| H A D | px30.c | 275 UART5_PLL_SEL_MASK | UART5_DIV_CON_MASK, in board_debug_uart_init()
|
| /dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/arch/arm/mach-rockchip/px30/ |
| H A D | px30.c | 275 UART5_PLL_SEL_MASK | UART5_DIV_CON_MASK, in board_debug_uart_init()
|
| /dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/arch/arm/mach-rockchip/px30/ |
| H A D | px30.c | 275 UART5_PLL_SEL_MASK | UART5_DIV_CON_MASK, in board_debug_uart_init()
|
| /dports/sysutils/u-boot-nanopi-neo/u-boot-2021.07/arch/arm/mach-rockchip/px30/ |
| H A D | px30.c | 275 UART5_PLL_SEL_MASK | UART5_DIV_CON_MASK, in board_debug_uart_init()
|
| /dports/sysutils/u-boot-nanopi-neo-air/u-boot-2021.07/arch/arm/mach-rockchip/px30/ |
| H A D | px30.c | 275 UART5_PLL_SEL_MASK | UART5_DIV_CON_MASK, in board_debug_uart_init()
|
| /dports/sysutils/u-boot-bananapi/u-boot-2021.07/arch/arm/mach-rockchip/px30/ |
| H A D | px30.c | 275 UART5_PLL_SEL_MASK | UART5_DIV_CON_MASK, in board_debug_uart_init()
|
| /dports/sysutils/u-boot-wandboard/u-boot-2021.07/arch/arm/mach-rockchip/px30/ |
| H A D | px30.c | 275 UART5_PLL_SEL_MASK | UART5_DIV_CON_MASK, in board_debug_uart_init()
|
| /dports/sysutils/u-boot-chip/u-boot-2021.07/arch/arm/mach-rockchip/px30/ |
| H A D | px30.c | 275 UART5_PLL_SEL_MASK | UART5_DIV_CON_MASK, in board_debug_uart_init()
|
| /dports/sysutils/u-boot-cubieboard/u-boot-2021.07/arch/arm/mach-rockchip/px30/ |
| H A D | px30.c | 275 UART5_PLL_SEL_MASK | UART5_DIV_CON_MASK, in board_debug_uart_init()
|
| /dports/sysutils/u-boot-clearfog/u-boot-2021.07/arch/arm/mach-rockchip/px30/ |
| H A D | px30.c | 275 UART5_PLL_SEL_MASK | UART5_DIV_CON_MASK, in board_debug_uart_init()
|
| /dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/arch/arm/mach-rockchip/px30/ |
| H A D | px30.c | 275 UART5_PLL_SEL_MASK | UART5_DIV_CON_MASK, in board_debug_uart_init()
|
| /dports/sysutils/u-boot-pandaboard/u-boot-2021.07/arch/arm/mach-rockchip/px30/ |
| H A D | px30.c | 275 UART5_PLL_SEL_MASK | UART5_DIV_CON_MASK, in board_debug_uart_init()
|
| /dports/sysutils/u-boot-orangepi-zero/u-boot-2021.07/arch/arm/mach-rockchip/px30/ |
| H A D | px30.c | 275 UART5_PLL_SEL_MASK | UART5_DIV_CON_MASK, in board_debug_uart_init()
|
| /dports/sysutils/u-boot-orangepi-r1/u-boot-2021.07/arch/arm/mach-rockchip/px30/ |
| H A D | px30.c | 275 UART5_PLL_SEL_MASK | UART5_DIV_CON_MASK, in board_debug_uart_init()
|
| /dports/sysutils/u-boot-orangepi-zero-plus/u-boot-2021.07/arch/arm/mach-rockchip/px30/ |
| H A D | px30.c | 275 UART5_PLL_SEL_MASK | UART5_DIV_CON_MASK, in board_debug_uart_init()
|
| /dports/sysutils/u-boot-pine-h64/u-boot-2021.07/arch/arm/mach-rockchip/px30/ |
| H A D | px30.c | 275 UART5_PLL_SEL_MASK | UART5_DIV_CON_MASK, in board_debug_uart_init()
|