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Searched refs:UART_CTL_REG (Results 1 – 25 of 68) sorted by relevance

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/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/tty/serial/
H A Dbcm63xx_uart.c112 val = bcm_uart_readl(port, UART_CTL_REG); in bcm_uart_set_mctrl()
117 bcm_uart_writel(port, val, UART_CTL_REG); in bcm_uart_set_mctrl()
147 val = bcm_uart_readl(port, UART_CTL_REG); in bcm_uart_stop_tx()
149 bcm_uart_writel(port, val, UART_CTL_REG); in bcm_uart_stop_tx()
167 val = bcm_uart_readl(port, UART_CTL_REG); in bcm_uart_start_tx()
169 bcm_uart_writel(port, val, UART_CTL_REG); in bcm_uart_start_tx()
206 val = bcm_uart_readl(port, UART_CTL_REG); in bcm_uart_break_ctl()
211 bcm_uart_writel(port, val, UART_CTL_REG); in bcm_uart_break_ctl()
396 val = bcm_uart_readl(port, UART_CTL_REG); in bcm_uart_enable()
398 bcm_uart_writel(port, val, UART_CTL_REG); in bcm_uart_enable()
[all …]
/dports/multimedia/libv4l/linux-5.13-rc2/drivers/tty/serial/
H A Dbcm63xx_uart.c112 val = bcm_uart_readl(port, UART_CTL_REG); in bcm_uart_set_mctrl()
117 bcm_uart_writel(port, val, UART_CTL_REG); in bcm_uart_set_mctrl()
147 val = bcm_uart_readl(port, UART_CTL_REG); in bcm_uart_stop_tx()
149 bcm_uart_writel(port, val, UART_CTL_REG); in bcm_uart_stop_tx()
167 val = bcm_uart_readl(port, UART_CTL_REG); in bcm_uart_start_tx()
169 bcm_uart_writel(port, val, UART_CTL_REG); in bcm_uart_start_tx()
206 val = bcm_uart_readl(port, UART_CTL_REG); in bcm_uart_break_ctl()
211 bcm_uart_writel(port, val, UART_CTL_REG); in bcm_uart_break_ctl()
396 val = bcm_uart_readl(port, UART_CTL_REG); in bcm_uart_enable()
398 bcm_uart_writel(port, val, UART_CTL_REG); in bcm_uart_enable()
[all …]
/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/tty/serial/
H A Dbcm63xx_uart.c112 val = bcm_uart_readl(port, UART_CTL_REG); in bcm_uart_set_mctrl()
117 bcm_uart_writel(port, val, UART_CTL_REG); in bcm_uart_set_mctrl()
147 val = bcm_uart_readl(port, UART_CTL_REG); in bcm_uart_stop_tx()
149 bcm_uart_writel(port, val, UART_CTL_REG); in bcm_uart_stop_tx()
167 val = bcm_uart_readl(port, UART_CTL_REG); in bcm_uart_start_tx()
169 bcm_uart_writel(port, val, UART_CTL_REG); in bcm_uart_start_tx()
206 val = bcm_uart_readl(port, UART_CTL_REG); in bcm_uart_break_ctl()
211 bcm_uart_writel(port, val, UART_CTL_REG); in bcm_uart_break_ctl()
396 val = bcm_uart_readl(port, UART_CTL_REG); in bcm_uart_enable()
398 bcm_uart_writel(port, val, UART_CTL_REG); in bcm_uart_enable()
[all …]
/dports/emulators/qemu42/qemu-4.2.1/roms/u-boot/drivers/serial/
H A Dserial_bcm6345.c18 #define UART_CTL_REG 0x0 macro
92 setbits_32(base + UART_CTL_REG, UART_CTL_BRGEN_MASK | in bcm6345_serial_enable()
99 clrbits_32(base + UART_CTL_REG, UART_CTL_BRGEN_MASK | in bcm6345_serial_disable()
107 setbits_32(base + UART_CTL_REG, UART_CTL_RSTRXFIFO_MASK | in bcm6345_serial_flush()
123 clrsetbits_32(base + UART_CTL_REG, in bcm6345_serial_init()
214 setbits_32(priv->base + UART_CTL_REG, UART_CTL_RSTRXFIFO_MASK); in bcm6345_serial_getc()
/dports/emulators/qemu5/qemu-5.2.0/roms/u-boot/drivers/serial/
H A Dserial_bcm6345.c18 #define UART_CTL_REG 0x0 macro
92 setbits_32(base + UART_CTL_REG, UART_CTL_BRGEN_MASK | in bcm6345_serial_enable()
99 clrbits_32(base + UART_CTL_REG, UART_CTL_BRGEN_MASK | in bcm6345_serial_disable()
107 setbits_32(base + UART_CTL_REG, UART_CTL_RSTRXFIFO_MASK | in bcm6345_serial_flush()
123 clrsetbits_32(base + UART_CTL_REG, in bcm6345_serial_init()
214 setbits_32(priv->base + UART_CTL_REG, UART_CTL_RSTRXFIFO_MASK); in bcm6345_serial_getc()
/dports/sysutils/u-boot-nanopi-neo2/u-boot-2021.07/drivers/serial/
H A Dserial_bcm6345.c19 #define UART_CTL_REG 0x0 macro
93 setbits_32(base + UART_CTL_REG, UART_CTL_BRGEN_MASK | in bcm6345_serial_enable()
100 clrbits_32(base + UART_CTL_REG, UART_CTL_BRGEN_MASK | in bcm6345_serial_disable()
108 setbits_32(base + UART_CTL_REG, UART_CTL_RSTRXFIFO_MASK | in bcm6345_serial_flush()
124 clrsetbits_32(base + UART_CTL_REG, in bcm6345_serial_init()
215 setbits_32(priv->base + UART_CTL_REG, UART_CTL_RSTRXFIFO_MASK); in bcm6345_serial_getc()
/dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/drivers/serial/
H A Dserial_bcm6345.c19 #define UART_CTL_REG 0x0 macro
93 setbits_32(base + UART_CTL_REG, UART_CTL_BRGEN_MASK | in bcm6345_serial_enable()
100 clrbits_32(base + UART_CTL_REG, UART_CTL_BRGEN_MASK | in bcm6345_serial_disable()
108 setbits_32(base + UART_CTL_REG, UART_CTL_RSTRXFIFO_MASK | in bcm6345_serial_flush()
124 clrsetbits_32(base + UART_CTL_REG, in bcm6345_serial_init()
215 setbits_32(priv->base + UART_CTL_REG, UART_CTL_RSTRXFIFO_MASK); in bcm6345_serial_getc()
/dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/drivers/serial/
H A Dserial_bcm6345.c19 #define UART_CTL_REG 0x0 macro
93 setbits_32(base + UART_CTL_REG, UART_CTL_BRGEN_MASK | in bcm6345_serial_enable()
100 clrbits_32(base + UART_CTL_REG, UART_CTL_BRGEN_MASK | in bcm6345_serial_disable()
108 setbits_32(base + UART_CTL_REG, UART_CTL_RSTRXFIFO_MASK | in bcm6345_serial_flush()
124 clrsetbits_32(base + UART_CTL_REG, in bcm6345_serial_init()
215 setbits_32(priv->base + UART_CTL_REG, UART_CTL_RSTRXFIFO_MASK); in bcm6345_serial_getc()
/dports/sysutils/u-boot-chip/u-boot-2021.07/drivers/serial/
H A Dserial_bcm6345.c19 #define UART_CTL_REG 0x0 macro
93 setbits_32(base + UART_CTL_REG, UART_CTL_BRGEN_MASK | in bcm6345_serial_enable()
100 clrbits_32(base + UART_CTL_REG, UART_CTL_BRGEN_MASK | in bcm6345_serial_disable()
108 setbits_32(base + UART_CTL_REG, UART_CTL_RSTRXFIFO_MASK | in bcm6345_serial_flush()
124 clrsetbits_32(base + UART_CTL_REG, in bcm6345_serial_init()
215 setbits_32(priv->base + UART_CTL_REG, UART_CTL_RSTRXFIFO_MASK); in bcm6345_serial_getc()
/dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/drivers/serial/
H A Dserial_bcm6345.c19 #define UART_CTL_REG 0x0 macro
93 setbits_32(base + UART_CTL_REG, UART_CTL_BRGEN_MASK | in bcm6345_serial_enable()
100 clrbits_32(base + UART_CTL_REG, UART_CTL_BRGEN_MASK | in bcm6345_serial_disable()
108 setbits_32(base + UART_CTL_REG, UART_CTL_RSTRXFIFO_MASK | in bcm6345_serial_flush()
124 clrsetbits_32(base + UART_CTL_REG, in bcm6345_serial_init()
215 setbits_32(priv->base + UART_CTL_REG, UART_CTL_RSTRXFIFO_MASK); in bcm6345_serial_getc()
/dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/drivers/serial/
H A Dserial_bcm6345.c19 #define UART_CTL_REG 0x0 macro
93 setbits_32(base + UART_CTL_REG, UART_CTL_BRGEN_MASK | in bcm6345_serial_enable()
100 clrbits_32(base + UART_CTL_REG, UART_CTL_BRGEN_MASK | in bcm6345_serial_disable()
108 setbits_32(base + UART_CTL_REG, UART_CTL_RSTRXFIFO_MASK | in bcm6345_serial_flush()
124 clrsetbits_32(base + UART_CTL_REG, in bcm6345_serial_init()
215 setbits_32(priv->base + UART_CTL_REG, UART_CTL_RSTRXFIFO_MASK); in bcm6345_serial_getc()
/dports/sysutils/u-boot-cubieboard/u-boot-2021.07/drivers/serial/
H A Dserial_bcm6345.c19 #define UART_CTL_REG 0x0 macro
93 setbits_32(base + UART_CTL_REG, UART_CTL_BRGEN_MASK | in bcm6345_serial_enable()
100 clrbits_32(base + UART_CTL_REG, UART_CTL_BRGEN_MASK | in bcm6345_serial_disable()
108 setbits_32(base + UART_CTL_REG, UART_CTL_RSTRXFIFO_MASK | in bcm6345_serial_flush()
124 clrsetbits_32(base + UART_CTL_REG, in bcm6345_serial_init()
215 setbits_32(priv->base + UART_CTL_REG, UART_CTL_RSTRXFIFO_MASK); in bcm6345_serial_getc()
/dports/sysutils/u-boot-firefly-rk3399/u-boot-2021.07/drivers/serial/
H A Dserial_bcm6345.c19 #define UART_CTL_REG 0x0 macro
93 setbits_32(base + UART_CTL_REG, UART_CTL_BRGEN_MASK | in bcm6345_serial_enable()
100 clrbits_32(base + UART_CTL_REG, UART_CTL_BRGEN_MASK | in bcm6345_serial_disable()
108 setbits_32(base + UART_CTL_REG, UART_CTL_RSTRXFIFO_MASK | in bcm6345_serial_flush()
124 clrsetbits_32(base + UART_CTL_REG, in bcm6345_serial_init()
215 setbits_32(priv->base + UART_CTL_REG, UART_CTL_RSTRXFIFO_MASK); in bcm6345_serial_getc()
/dports/sysutils/u-boot-sinovoip-bpi-m3/u-boot-2021.07/drivers/serial/
H A Dserial_bcm6345.c19 #define UART_CTL_REG 0x0 macro
93 setbits_32(base + UART_CTL_REG, UART_CTL_BRGEN_MASK | in bcm6345_serial_enable()
100 clrbits_32(base + UART_CTL_REG, UART_CTL_BRGEN_MASK | in bcm6345_serial_disable()
108 setbits_32(base + UART_CTL_REG, UART_CTL_RSTRXFIFO_MASK | in bcm6345_serial_flush()
124 clrsetbits_32(base + UART_CTL_REG, in bcm6345_serial_init()
215 setbits_32(priv->base + UART_CTL_REG, UART_CTL_RSTRXFIFO_MASK); in bcm6345_serial_getc()
/dports/sysutils/u-boot-a13-olinuxino/u-boot-2021.07/drivers/serial/
H A Dserial_bcm6345.c19 #define UART_CTL_REG 0x0 macro
93 setbits_32(base + UART_CTL_REG, UART_CTL_BRGEN_MASK | in bcm6345_serial_enable()
100 clrbits_32(base + UART_CTL_REG, UART_CTL_BRGEN_MASK | in bcm6345_serial_disable()
108 setbits_32(base + UART_CTL_REG, UART_CTL_RSTRXFIFO_MASK | in bcm6345_serial_flush()
124 clrsetbits_32(base + UART_CTL_REG, in bcm6345_serial_init()
215 setbits_32(priv->base + UART_CTL_REG, UART_CTL_RSTRXFIFO_MASK); in bcm6345_serial_getc()
/dports/sysutils/u-boot-sopine/u-boot-2021.07/drivers/serial/
H A Dserial_bcm6345.c19 #define UART_CTL_REG 0x0 macro
93 setbits_32(base + UART_CTL_REG, UART_CTL_BRGEN_MASK | in bcm6345_serial_enable()
100 clrbits_32(base + UART_CTL_REG, UART_CTL_BRGEN_MASK | in bcm6345_serial_disable()
108 setbits_32(base + UART_CTL_REG, UART_CTL_RSTRXFIFO_MASK | in bcm6345_serial_flush()
124 clrsetbits_32(base + UART_CTL_REG, in bcm6345_serial_init()
215 setbits_32(priv->base + UART_CTL_REG, UART_CTL_RSTRXFIFO_MASK); in bcm6345_serial_getc()
/dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/drivers/serial/
H A Dserial_bcm6345.c19 #define UART_CTL_REG 0x0 macro
93 setbits_32(base + UART_CTL_REG, UART_CTL_BRGEN_MASK | in bcm6345_serial_enable()
100 clrbits_32(base + UART_CTL_REG, UART_CTL_BRGEN_MASK | in bcm6345_serial_disable()
108 setbits_32(base + UART_CTL_REG, UART_CTL_RSTRXFIFO_MASK | in bcm6345_serial_flush()
124 clrsetbits_32(base + UART_CTL_REG, in bcm6345_serial_init()
215 setbits_32(priv->base + UART_CTL_REG, UART_CTL_RSTRXFIFO_MASK); in bcm6345_serial_getc()
/dports/sysutils/u-boot-rpi/u-boot-2021.07/drivers/serial/
H A Dserial_bcm6345.c19 #define UART_CTL_REG 0x0 macro
93 setbits_32(base + UART_CTL_REG, UART_CTL_BRGEN_MASK | in bcm6345_serial_enable()
100 clrbits_32(base + UART_CTL_REG, UART_CTL_BRGEN_MASK | in bcm6345_serial_disable()
108 setbits_32(base + UART_CTL_REG, UART_CTL_RSTRXFIFO_MASK | in bcm6345_serial_flush()
124 clrsetbits_32(base + UART_CTL_REG, in bcm6345_serial_init()
215 setbits_32(priv->base + UART_CTL_REG, UART_CTL_RSTRXFIFO_MASK); in bcm6345_serial_getc()
/dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/drivers/serial/
H A Dserial_bcm6345.c19 #define UART_CTL_REG 0x0 macro
93 setbits_32(base + UART_CTL_REG, UART_CTL_BRGEN_MASK | in bcm6345_serial_enable()
100 clrbits_32(base + UART_CTL_REG, UART_CTL_BRGEN_MASK | in bcm6345_serial_disable()
108 setbits_32(base + UART_CTL_REG, UART_CTL_RSTRXFIFO_MASK | in bcm6345_serial_flush()
124 clrsetbits_32(base + UART_CTL_REG, in bcm6345_serial_init()
215 setbits_32(priv->base + UART_CTL_REG, UART_CTL_RSTRXFIFO_MASK); in bcm6345_serial_getc()
/dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/drivers/serial/
H A Dserial_bcm6345.c19 #define UART_CTL_REG 0x0 macro
93 setbits_32(base + UART_CTL_REG, UART_CTL_BRGEN_MASK | in bcm6345_serial_enable()
100 clrbits_32(base + UART_CTL_REG, UART_CTL_BRGEN_MASK | in bcm6345_serial_disable()
108 setbits_32(base + UART_CTL_REG, UART_CTL_RSTRXFIFO_MASK | in bcm6345_serial_flush()
124 clrsetbits_32(base + UART_CTL_REG, in bcm6345_serial_init()
215 setbits_32(priv->base + UART_CTL_REG, UART_CTL_RSTRXFIFO_MASK); in bcm6345_serial_getc()
/dports/sysutils/u-boot-nanopi-m1plus/u-boot-2021.07/drivers/serial/
H A Dserial_bcm6345.c19 #define UART_CTL_REG 0x0 macro
93 setbits_32(base + UART_CTL_REG, UART_CTL_BRGEN_MASK | in bcm6345_serial_enable()
100 clrbits_32(base + UART_CTL_REG, UART_CTL_BRGEN_MASK | in bcm6345_serial_disable()
108 setbits_32(base + UART_CTL_REG, UART_CTL_RSTRXFIFO_MASK | in bcm6345_serial_flush()
124 clrsetbits_32(base + UART_CTL_REG, in bcm6345_serial_init()
215 setbits_32(priv->base + UART_CTL_REG, UART_CTL_RSTRXFIFO_MASK); in bcm6345_serial_getc()
/dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/drivers/serial/
H A Dserial_bcm6345.c19 #define UART_CTL_REG 0x0 macro
93 setbits_32(base + UART_CTL_REG, UART_CTL_BRGEN_MASK | in bcm6345_serial_enable()
100 clrbits_32(base + UART_CTL_REG, UART_CTL_BRGEN_MASK | in bcm6345_serial_disable()
108 setbits_32(base + UART_CTL_REG, UART_CTL_RSTRXFIFO_MASK | in bcm6345_serial_flush()
124 clrsetbits_32(base + UART_CTL_REG, in bcm6345_serial_init()
215 setbits_32(priv->base + UART_CTL_REG, UART_CTL_RSTRXFIFO_MASK); in bcm6345_serial_getc()
/dports/sysutils/u-boot-beaglebone/u-boot-2021.07/drivers/serial/
H A Dserial_bcm6345.c19 #define UART_CTL_REG 0x0 macro
93 setbits_32(base + UART_CTL_REG, UART_CTL_BRGEN_MASK | in bcm6345_serial_enable()
100 clrbits_32(base + UART_CTL_REG, UART_CTL_BRGEN_MASK | in bcm6345_serial_disable()
108 setbits_32(base + UART_CTL_REG, UART_CTL_RSTRXFIFO_MASK | in bcm6345_serial_flush()
124 clrsetbits_32(base + UART_CTL_REG, in bcm6345_serial_init()
215 setbits_32(priv->base + UART_CTL_REG, UART_CTL_RSTRXFIFO_MASK); in bcm6345_serial_getc()
/dports/sysutils/u-boot-wandboard/u-boot-2021.07/drivers/serial/
H A Dserial_bcm6345.c19 #define UART_CTL_REG 0x0 macro
93 setbits_32(base + UART_CTL_REG, UART_CTL_BRGEN_MASK | in bcm6345_serial_enable()
100 clrbits_32(base + UART_CTL_REG, UART_CTL_BRGEN_MASK | in bcm6345_serial_disable()
108 setbits_32(base + UART_CTL_REG, UART_CTL_RSTRXFIFO_MASK | in bcm6345_serial_flush()
124 clrsetbits_32(base + UART_CTL_REG, in bcm6345_serial_init()
215 setbits_32(priv->base + UART_CTL_REG, UART_CTL_RSTRXFIFO_MASK); in bcm6345_serial_getc()
/dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot/drivers/serial/
H A Dserial_bcm6345.c18 #define UART_CTL_REG 0x0 macro
92 setbits_32(base + UART_CTL_REG, UART_CTL_BRGEN_MASK | in bcm6345_serial_enable()
99 clrbits_32(base + UART_CTL_REG, UART_CTL_BRGEN_MASK | in bcm6345_serial_disable()
107 setbits_32(base + UART_CTL_REG, UART_CTL_RSTRXFIFO_MASK | in bcm6345_serial_flush()
123 clrsetbits_32(base + UART_CTL_REG, in bcm6345_serial_init()
214 setbits_32(priv->base + UART_CTL_REG, UART_CTL_RSTRXFIFO_MASK); in bcm6345_serial_getc()

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