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Searched refs:UNIPHIER_UART_DLR (Results 1 – 25 of 69) sorted by relevance

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/dports/multimedia/libv4l/linux-5.13-rc2/drivers/tty/serial/8250/
H A D8250_uniphier.c31 #define UNIPHIER_UART_DLR (9 << (UNIPHIER_UART_REGSHIFT)) macro
150 return readl(up->port.membase + UNIPHIER_UART_DLR); in uniphier_serial_dl_read()
155 writel(value, up->port.membase + UNIPHIER_UART_DLR); in uniphier_serial_dl_write()
/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/tty/serial/8250/
H A D8250_uniphier.c31 #define UNIPHIER_UART_DLR (9 << (UNIPHIER_UART_REGSHIFT)) macro
150 return readl(up->port.membase + UNIPHIER_UART_DLR); in uniphier_serial_dl_read()
155 writel(value, up->port.membase + UNIPHIER_UART_DLR); in uniphier_serial_dl_write()
/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/tty/serial/8250/
H A D8250_uniphier.c31 #define UNIPHIER_UART_DLR (9 << (UNIPHIER_UART_REGSHIFT)) macro
150 return readl(up->port.membase + UNIPHIER_UART_DLR); in uniphier_serial_dl_read()
155 writel(value, up->port.membase + UNIPHIER_UART_DLR); in uniphier_serial_dl_write()
/dports/sysutils/u-boot-nanopi-neo2/u-boot-2021.07/drivers/serial/
H A Dserial_uniphier.c32 #define UNIPHIER_UART_DLR (9 << (UNIPHIER_UART_REGSHIFT)) macro
51 writel(divisor, priv->membase + UNIPHIER_UART_DLR); in uniphier_serial_setbrg()
/dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/drivers/serial/
H A Dserial_uniphier.c32 #define UNIPHIER_UART_DLR (9 << (UNIPHIER_UART_REGSHIFT)) macro
51 writel(divisor, priv->membase + UNIPHIER_UART_DLR); in uniphier_serial_setbrg()
/dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/drivers/serial/
H A Dserial_uniphier.c32 #define UNIPHIER_UART_DLR (9 << (UNIPHIER_UART_REGSHIFT)) macro
51 writel(divisor, priv->membase + UNIPHIER_UART_DLR); in uniphier_serial_setbrg()
/dports/sysutils/u-boot-chip/u-boot-2021.07/drivers/serial/
H A Dserial_uniphier.c32 #define UNIPHIER_UART_DLR (9 << (UNIPHIER_UART_REGSHIFT)) macro
51 writel(divisor, priv->membase + UNIPHIER_UART_DLR); in uniphier_serial_setbrg()
/dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/drivers/serial/
H A Dserial_uniphier.c32 #define UNIPHIER_UART_DLR (9 << (UNIPHIER_UART_REGSHIFT)) macro
51 writel(divisor, priv->membase + UNIPHIER_UART_DLR); in uniphier_serial_setbrg()
/dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/drivers/serial/
H A Dserial_uniphier.c32 #define UNIPHIER_UART_DLR (9 << (UNIPHIER_UART_REGSHIFT)) macro
51 writel(divisor, priv->membase + UNIPHIER_UART_DLR); in uniphier_serial_setbrg()
/dports/sysutils/u-boot-cubieboard/u-boot-2021.07/drivers/serial/
H A Dserial_uniphier.c32 #define UNIPHIER_UART_DLR (9 << (UNIPHIER_UART_REGSHIFT)) macro
51 writel(divisor, priv->membase + UNIPHIER_UART_DLR); in uniphier_serial_setbrg()
/dports/sysutils/u-boot-firefly-rk3399/u-boot-2021.07/drivers/serial/
H A Dserial_uniphier.c32 #define UNIPHIER_UART_DLR (9 << (UNIPHIER_UART_REGSHIFT)) macro
51 writel(divisor, priv->membase + UNIPHIER_UART_DLR); in uniphier_serial_setbrg()
/dports/sysutils/u-boot-a13-olinuxino/u-boot-2021.07/drivers/serial/
H A Dserial_uniphier.c32 #define UNIPHIER_UART_DLR (9 << (UNIPHIER_UART_REGSHIFT)) macro
51 writel(divisor, priv->membase + UNIPHIER_UART_DLR); in uniphier_serial_setbrg()
/dports/sysutils/u-boot-sinovoip-bpi-m3/u-boot-2021.07/drivers/serial/
H A Dserial_uniphier.c32 #define UNIPHIER_UART_DLR (9 << (UNIPHIER_UART_REGSHIFT)) macro
51 writel(divisor, priv->membase + UNIPHIER_UART_DLR); in uniphier_serial_setbrg()
/dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/drivers/serial/
H A Dserial_uniphier.c32 #define UNIPHIER_UART_DLR (9 << (UNIPHIER_UART_REGSHIFT)) macro
51 writel(divisor, priv->membase + UNIPHIER_UART_DLR); in uniphier_serial_setbrg()
/dports/sysutils/u-boot-sopine/u-boot-2021.07/drivers/serial/
H A Dserial_uniphier.c32 #define UNIPHIER_UART_DLR (9 << (UNIPHIER_UART_REGSHIFT)) macro
51 writel(divisor, priv->membase + UNIPHIER_UART_DLR); in uniphier_serial_setbrg()
/dports/sysutils/u-boot-rpi/u-boot-2021.07/drivers/serial/
H A Dserial_uniphier.c32 #define UNIPHIER_UART_DLR (9 << (UNIPHIER_UART_REGSHIFT)) macro
51 writel(divisor, priv->membase + UNIPHIER_UART_DLR); in uniphier_serial_setbrg()
/dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/drivers/serial/
H A Dserial_uniphier.c32 #define UNIPHIER_UART_DLR (9 << (UNIPHIER_UART_REGSHIFT)) macro
51 writel(divisor, priv->membase + UNIPHIER_UART_DLR); in uniphier_serial_setbrg()
/dports/sysutils/u-boot-pinebookpro/u-boot-2021.07/drivers/serial/
H A Dserial_uniphier.c32 #define UNIPHIER_UART_DLR (9 << (UNIPHIER_UART_REGSHIFT)) macro
51 writel(divisor, priv->membase + UNIPHIER_UART_DLR); in uniphier_serial_setbrg()
/dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/drivers/serial/
H A Dserial_uniphier.c32 #define UNIPHIER_UART_DLR (9 << (UNIPHIER_UART_REGSHIFT)) macro
51 writel(divisor, priv->membase + UNIPHIER_UART_DLR); in uniphier_serial_setbrg()
/dports/sysutils/u-boot-nanopi-m1plus/u-boot-2021.07/drivers/serial/
H A Dserial_uniphier.c32 #define UNIPHIER_UART_DLR (9 << (UNIPHIER_UART_REGSHIFT)) macro
51 writel(divisor, priv->membase + UNIPHIER_UART_DLR); in uniphier_serial_setbrg()
/dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/drivers/serial/
H A Dserial_uniphier.c32 #define UNIPHIER_UART_DLR (9 << (UNIPHIER_UART_REGSHIFT)) macro
51 writel(divisor, priv->membase + UNIPHIER_UART_DLR); in uniphier_serial_setbrg()
/dports/sysutils/u-boot-beaglebone/u-boot-2021.07/drivers/serial/
H A Dserial_uniphier.c32 #define UNIPHIER_UART_DLR (9 << (UNIPHIER_UART_REGSHIFT)) macro
51 writel(divisor, priv->membase + UNIPHIER_UART_DLR); in uniphier_serial_setbrg()
/dports/sysutils/u-boot-wandboard/u-boot-2021.07/drivers/serial/
H A Dserial_uniphier.c32 #define UNIPHIER_UART_DLR (9 << (UNIPHIER_UART_REGSHIFT)) macro
51 writel(divisor, priv->membase + UNIPHIER_UART_DLR); in uniphier_serial_setbrg()
/dports/sysutils/u-boot-clearfog/u-boot-2021.07/drivers/serial/
H A Dserial_uniphier.c32 #define UNIPHIER_UART_DLR (9 << (UNIPHIER_UART_REGSHIFT)) macro
51 writel(divisor, priv->membase + UNIPHIER_UART_DLR); in uniphier_serial_setbrg()
/dports/sysutils/u-boot-orangepi-zero-plus/u-boot-2021.07/drivers/serial/
H A Dserial_uniphier.c32 #define UNIPHIER_UART_DLR (9 << (UNIPHIER_UART_REGSHIFT)) macro
51 writel(divisor, priv->membase + UNIPHIER_UART_DLR); in uniphier_serial_setbrg()

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