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Searched refs:UVD_MPC_SET_MUXA1__VARA_7__SHIFT (Results 1 – 25 of 33) sorted by relevance

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/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_7_0_sh_mask.h611 #define UVD_MPC_SET_MUXA1__VARA_7__SHIFT macro
H A Duvd_4_2_sh_mask.h496 #define UVD_MPC_SET_MUXA1__VARA_7__SHIFT 0xc macro
H A Duvd_4_0_sh_mask.h511 #define UVD_MPC_SET_MUXA1__VARA_7__SHIFT 0x0000000c macro
H A Duvd_3_1_sh_mask.h492 #define UVD_MPC_SET_MUXA1__VARA_7__SHIFT 0xc macro
H A Duvd_5_0_sh_mask.h528 #define UVD_MPC_SET_MUXA1__VARA_7__SHIFT 0xc macro
H A Duvd_6_0_sh_mask.h530 #define UVD_MPC_SET_MUXA1__VARA_7__SHIFT 0xc macro
/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_7_0_sh_mask.h611 #define UVD_MPC_SET_MUXA1__VARA_7__SHIFT macro
H A Duvd_3_1_sh_mask.h492 #define UVD_MPC_SET_MUXA1__VARA_7__SHIFT 0xc macro
H A Duvd_4_0_sh_mask.h511 #define UVD_MPC_SET_MUXA1__VARA_7__SHIFT 0x0000000c macro
H A Duvd_4_2_sh_mask.h496 #define UVD_MPC_SET_MUXA1__VARA_7__SHIFT 0xc macro
H A Duvd_5_0_sh_mask.h528 #define UVD_MPC_SET_MUXA1__VARA_7__SHIFT 0xc macro
H A Duvd_6_0_sh_mask.h530 #define UVD_MPC_SET_MUXA1__VARA_7__SHIFT 0xc macro
/dports/multimedia/libv4l/linux-5.13-rc2/drivers/gpu/drm/amd/include/asic_reg/uvd/
H A Duvd_7_0_sh_mask.h611 #define UVD_MPC_SET_MUXA1__VARA_7__SHIFT macro
H A Duvd_3_1_sh_mask.h492 #define UVD_MPC_SET_MUXA1__VARA_7__SHIFT 0xc macro
H A Duvd_4_0_sh_mask.h511 #define UVD_MPC_SET_MUXA1__VARA_7__SHIFT 0x0000000c macro
H A Duvd_4_2_sh_mask.h496 #define UVD_MPC_SET_MUXA1__VARA_7__SHIFT 0xc macro
H A Duvd_5_0_sh_mask.h528 #define UVD_MPC_SET_MUXA1__VARA_7__SHIFT 0xc macro
H A Duvd_6_0_sh_mask.h530 #define UVD_MPC_SET_MUXA1__VARA_7__SHIFT 0xc macro
/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_sh_mask.h1118 #define UVD_MPC_SET_MUXA1__VARA_7__SHIFT macro
H A Dvcn_2_5_sh_mask.h2859 #define UVD_MPC_SET_MUXA1__VARA_7__SHIFT macro
H A Dvcn_2_0_0_sh_mask.h2624 #define UVD_MPC_SET_MUXA1__VARA_7__SHIFT macro
/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_sh_mask.h1118 #define UVD_MPC_SET_MUXA1__VARA_7__SHIFT macro
H A Dvcn_2_5_sh_mask.h2859 #define UVD_MPC_SET_MUXA1__VARA_7__SHIFT macro
/dports/multimedia/libv4l/linux-5.13-rc2/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_1_0_sh_mask.h1118 #define UVD_MPC_SET_MUXA1__VARA_7__SHIFT macro
H A Dvcn_2_5_sh_mask.h2859 #define UVD_MPC_SET_MUXA1__VARA_7__SHIFT macro

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