| /dports/emulators/qemu42/qemu-4.2.1/roms/edk2/MdeModulePkg/Bus/Pci/UhciPei/ |
| H A D | UhcPeim.c | 33 CommandContent = USBReadPortW (Uhc, Uhc->UsbHostControllerBaseAddress + USBCMD); in UhciStopHc()
35 USBWritePortW (Uhc, Uhc->UsbHostControllerBaseAddress + USBCMD, CommandContent); in UhciStopHc()
42 UsbSts = USBReadPortW (Uhc, Uhc->UsbHostControllerBaseAddress + USBSTS); in UhciStopHc()
167 UhcDev->UsbHostControllerBaseAddress = (UINT32) BaseAddress; in UhcPeimEntry()
273 StatusReg = UhcDev->UsbHostControllerBaseAddress + USBSTS; in UhcControlTransfer()
534 StatusReg = UhcDev->UsbHostControllerBaseAddress + USBSTS; in UhcBulkTransfer()
720 PSAddr = UhcDev->UsbHostControllerBaseAddress + USBPORTSC1 + Index * 2; in UhcGetRootHubPortNumber()
861 CommandRegAddr = UhcDev->UsbHostControllerBaseAddress + USBCMD; in UhcSetRootHubPortFeature()
938 PSAddr = UhcDev->UsbHostControllerBaseAddress + USBPORTSC1 + PortNumber * 2; in UhcClearRootHubPortFeature()
1044 FrameListBaseAddrReg = UhcDev->UsbHostControllerBaseAddress + USBFLBASEADD; in InitializeUsbHC()
[all …]
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| /dports/emulators/qemu/qemu-6.2.0/roms/edk2/MdeModulePkg/Bus/Pci/UhciPei/ |
| H A D | UhcPeim.c | 33 CommandContent = USBReadPortW (Uhc, Uhc->UsbHostControllerBaseAddress + USBCMD); in UhciStopHc()
35 USBWritePortW (Uhc, Uhc->UsbHostControllerBaseAddress + USBCMD, CommandContent); in UhciStopHc()
42 UsbSts = USBReadPortW (Uhc, Uhc->UsbHostControllerBaseAddress + USBSTS); in UhciStopHc()
167 UhcDev->UsbHostControllerBaseAddress = (UINT32) BaseAddress; in UhcPeimEntry()
273 StatusReg = UhcDev->UsbHostControllerBaseAddress + USBSTS; in UhcControlTransfer()
536 StatusReg = UhcDev->UsbHostControllerBaseAddress + USBSTS; in UhcBulkTransfer()
722 PSAddr = UhcDev->UsbHostControllerBaseAddress + USBPORTSC1 + Index * 2; in UhcGetRootHubPortNumber()
863 CommandRegAddr = UhcDev->UsbHostControllerBaseAddress + USBCMD; in UhcSetRootHubPortFeature()
940 PSAddr = UhcDev->UsbHostControllerBaseAddress + USBPORTSC1 + PortNumber * 2; in UhcClearRootHubPortFeature()
1046 FrameListBaseAddrReg = UhcDev->UsbHostControllerBaseAddress + USBFLBASEADD; in InitializeUsbHC()
[all …]
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| /dports/emulators/qemu5/qemu-5.2.0/roms/edk2/MdeModulePkg/Bus/Pci/UhciPei/ |
| H A D | UhcPeim.c | 33 CommandContent = USBReadPortW (Uhc, Uhc->UsbHostControllerBaseAddress + USBCMD); in UhciStopHc()
35 USBWritePortW (Uhc, Uhc->UsbHostControllerBaseAddress + USBCMD, CommandContent); in UhciStopHc()
42 UsbSts = USBReadPortW (Uhc, Uhc->UsbHostControllerBaseAddress + USBSTS); in UhciStopHc()
167 UhcDev->UsbHostControllerBaseAddress = (UINT32) BaseAddress; in UhcPeimEntry()
273 StatusReg = UhcDev->UsbHostControllerBaseAddress + USBSTS; in UhcControlTransfer()
536 StatusReg = UhcDev->UsbHostControllerBaseAddress + USBSTS; in UhcBulkTransfer()
722 PSAddr = UhcDev->UsbHostControllerBaseAddress + USBPORTSC1 + Index * 2; in UhcGetRootHubPortNumber()
863 CommandRegAddr = UhcDev->UsbHostControllerBaseAddress + USBCMD; in UhcSetRootHubPortFeature()
940 PSAddr = UhcDev->UsbHostControllerBaseAddress + USBPORTSC1 + PortNumber * 2; in UhcClearRootHubPortFeature()
1046 FrameListBaseAddrReg = UhcDev->UsbHostControllerBaseAddress + USBFLBASEADD; in InitializeUsbHC()
[all …]
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| /dports/emulators/qemu60/qemu-6.0.0/roms/edk2/MdeModulePkg/Bus/Pci/UhciPei/ |
| H A D | UhcPeim.c | 33 CommandContent = USBReadPortW (Uhc, Uhc->UsbHostControllerBaseAddress + USBCMD); in UhciStopHc()
35 USBWritePortW (Uhc, Uhc->UsbHostControllerBaseAddress + USBCMD, CommandContent); in UhciStopHc()
42 UsbSts = USBReadPortW (Uhc, Uhc->UsbHostControllerBaseAddress + USBSTS); in UhciStopHc()
167 UhcDev->UsbHostControllerBaseAddress = (UINT32) BaseAddress; in UhcPeimEntry()
273 StatusReg = UhcDev->UsbHostControllerBaseAddress + USBSTS; in UhcControlTransfer()
536 StatusReg = UhcDev->UsbHostControllerBaseAddress + USBSTS; in UhcBulkTransfer()
722 PSAddr = UhcDev->UsbHostControllerBaseAddress + USBPORTSC1 + Index * 2; in UhcGetRootHubPortNumber()
863 CommandRegAddr = UhcDev->UsbHostControllerBaseAddress + USBCMD; in UhcSetRootHubPortFeature()
940 PSAddr = UhcDev->UsbHostControllerBaseAddress + USBPORTSC1 + PortNumber * 2; in UhcClearRootHubPortFeature()
1046 FrameListBaseAddrReg = UhcDev->UsbHostControllerBaseAddress + USBFLBASEADD; in InitializeUsbHC()
[all …]
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| /dports/emulators/qemu-utils/qemu-4.2.1/roms/edk2/MdeModulePkg/Bus/Pci/UhciPei/ |
| H A D | UhcPeim.c | 33 CommandContent = USBReadPortW (Uhc, Uhc->UsbHostControllerBaseAddress + USBCMD); in UhciStopHc()
35 USBWritePortW (Uhc, Uhc->UsbHostControllerBaseAddress + USBCMD, CommandContent); in UhciStopHc()
42 UsbSts = USBReadPortW (Uhc, Uhc->UsbHostControllerBaseAddress + USBSTS); in UhciStopHc()
167 UhcDev->UsbHostControllerBaseAddress = (UINT32) BaseAddress; in UhcPeimEntry()
273 StatusReg = UhcDev->UsbHostControllerBaseAddress + USBSTS; in UhcControlTransfer()
534 StatusReg = UhcDev->UsbHostControllerBaseAddress + USBSTS; in UhcBulkTransfer()
720 PSAddr = UhcDev->UsbHostControllerBaseAddress + USBPORTSC1 + Index * 2; in UhcGetRootHubPortNumber()
861 CommandRegAddr = UhcDev->UsbHostControllerBaseAddress + USBCMD; in UhcSetRootHubPortFeature()
938 PSAddr = UhcDev->UsbHostControllerBaseAddress + USBPORTSC1 + PortNumber * 2; in UhcClearRootHubPortFeature()
1044 FrameListBaseAddrReg = UhcDev->UsbHostControllerBaseAddress + USBFLBASEADD; in InitializeUsbHC()
[all …]
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| /dports/sysutils/uefi-edk2-qemu/edk2-edk2-stable201911/MdeModulePkg/Bus/Pci/UhciPei/ |
| H A D | UhcPeim.c | 33 CommandContent = USBReadPortW (Uhc, Uhc->UsbHostControllerBaseAddress + USBCMD); in UhciStopHc()
35 USBWritePortW (Uhc, Uhc->UsbHostControllerBaseAddress + USBCMD, CommandContent); in UhciStopHc()
42 UsbSts = USBReadPortW (Uhc, Uhc->UsbHostControllerBaseAddress + USBSTS); in UhciStopHc()
167 UhcDev->UsbHostControllerBaseAddress = (UINT32) BaseAddress; in UhcPeimEntry()
273 StatusReg = UhcDev->UsbHostControllerBaseAddress + USBSTS; in UhcControlTransfer()
536 StatusReg = UhcDev->UsbHostControllerBaseAddress + USBSTS; in UhcBulkTransfer()
722 PSAddr = UhcDev->UsbHostControllerBaseAddress + USBPORTSC1 + Index * 2; in UhcGetRootHubPortNumber()
863 CommandRegAddr = UhcDev->UsbHostControllerBaseAddress + USBCMD; in UhcSetRootHubPortFeature()
940 PSAddr = UhcDev->UsbHostControllerBaseAddress + USBPORTSC1 + PortNumber * 2; in UhcClearRootHubPortFeature()
1046 FrameListBaseAddrReg = UhcDev->UsbHostControllerBaseAddress + USBFLBASEADD; in InitializeUsbHC()
[all …]
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| /dports/sysutils/uefi-edk2-bhyve/edk2-edk2-stable202102/MdeModulePkg/Bus/Pci/UhciPei/ |
| H A D | UhcPeim.c | 33 CommandContent = USBReadPortW (Uhc, Uhc->UsbHostControllerBaseAddress + USBCMD); in UhciStopHc()
35 USBWritePortW (Uhc, Uhc->UsbHostControllerBaseAddress + USBCMD, CommandContent); in UhciStopHc()
42 UsbSts = USBReadPortW (Uhc, Uhc->UsbHostControllerBaseAddress + USBSTS); in UhciStopHc()
167 UhcDev->UsbHostControllerBaseAddress = (UINT32) BaseAddress; in UhcPeimEntry()
273 StatusReg = UhcDev->UsbHostControllerBaseAddress + USBSTS; in UhcControlTransfer()
536 StatusReg = UhcDev->UsbHostControllerBaseAddress + USBSTS; in UhcBulkTransfer()
722 PSAddr = UhcDev->UsbHostControllerBaseAddress + USBPORTSC1 + Index * 2; in UhcGetRootHubPortNumber()
863 CommandRegAddr = UhcDev->UsbHostControllerBaseAddress + USBCMD; in UhcSetRootHubPortFeature()
940 PSAddr = UhcDev->UsbHostControllerBaseAddress + USBPORTSC1 + PortNumber * 2; in UhcClearRootHubPortFeature()
1046 FrameListBaseAddrReg = UhcDev->UsbHostControllerBaseAddress + USBFLBASEADD; in InitializeUsbHC()
[all …]
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| /dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/edk2/MdeModulePkg/Bus/Pci/UhciPei/ |
| H A D | UhcPeim.c | 33 CommandContent = USBReadPortW (Uhc, Uhc->UsbHostControllerBaseAddress + USBCMD); in UhciStopHc()
35 USBWritePortW (Uhc, Uhc->UsbHostControllerBaseAddress + USBCMD, CommandContent); in UhciStopHc()
42 UsbSts = USBReadPortW (Uhc, Uhc->UsbHostControllerBaseAddress + USBSTS); in UhciStopHc()
167 UhcDev->UsbHostControllerBaseAddress = (UINT32) BaseAddress; in UhcPeimEntry()
273 StatusReg = UhcDev->UsbHostControllerBaseAddress + USBSTS; in UhcControlTransfer()
534 StatusReg = UhcDev->UsbHostControllerBaseAddress + USBSTS; in UhcBulkTransfer()
720 PSAddr = UhcDev->UsbHostControllerBaseAddress + USBPORTSC1 + Index * 2; in UhcGetRootHubPortNumber()
861 CommandRegAddr = UhcDev->UsbHostControllerBaseAddress + USBCMD; in UhcSetRootHubPortFeature()
938 PSAddr = UhcDev->UsbHostControllerBaseAddress + USBPORTSC1 + PortNumber * 2; in UhcClearRootHubPortFeature()
1044 FrameListBaseAddrReg = UhcDev->UsbHostControllerBaseAddress + USBFLBASEADD; in InitializeUsbHC()
[all …]
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| /dports/sysutils/edk2/edk2-edk2-stable202102/MdeModulePkg/Bus/Pci/UhciPei/ |
| H A D | UhcPeim.c | 33 CommandContent = USBReadPortW (Uhc, Uhc->UsbHostControllerBaseAddress + USBCMD); in UhciStopHc()
35 USBWritePortW (Uhc, Uhc->UsbHostControllerBaseAddress + USBCMD, CommandContent); in UhciStopHc()
42 UsbSts = USBReadPortW (Uhc, Uhc->UsbHostControllerBaseAddress + USBSTS); in UhciStopHc()
167 UhcDev->UsbHostControllerBaseAddress = (UINT32) BaseAddress; in UhcPeimEntry()
273 StatusReg = UhcDev->UsbHostControllerBaseAddress + USBSTS; in UhcControlTransfer()
536 StatusReg = UhcDev->UsbHostControllerBaseAddress + USBSTS; in UhcBulkTransfer()
722 PSAddr = UhcDev->UsbHostControllerBaseAddress + USBPORTSC1 + Index * 2; in UhcGetRootHubPortNumber()
863 CommandRegAddr = UhcDev->UsbHostControllerBaseAddress + USBCMD; in UhcSetRootHubPortFeature()
940 PSAddr = UhcDev->UsbHostControllerBaseAddress + USBPORTSC1 + PortNumber * 2; in UhcClearRootHubPortFeature()
1046 FrameListBaseAddrReg = UhcDev->UsbHostControllerBaseAddress + USBFLBASEADD; in InitializeUsbHC()
[all …]
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| /dports/sysutils/uefi-edk2-bhyve-csm/uefi-edk2-aa8d718/MdeModulePkg/Bus/Pci/XhciPei/ |
| H A D | XhcPeim.c | 88 Data = MmioRead32 (Xhc->UsbHostControllerBaseAddress + Xhc->CapLength + Offset); in XhcPeiReadOpReg()
109 MmioWrite32 (Xhc->UsbHostControllerBaseAddress + Xhc->CapLength + Offset, Data); in XhcPeiWriteOpReg()
209 Data = MmioRead32 (Xhc->UsbHostControllerBaseAddress + Offset); in XhcPeiReadCapRegister()
233 Data = MmioRead32 (Xhc->UsbHostControllerBaseAddress + Xhc->DBOff + Offset); in XhcPeiReadDoorBellReg()
255 MmioWrite32 (Xhc->UsbHostControllerBaseAddress + Xhc->DBOff + Offset, Data); in XhcPeiWriteDoorBellReg()
277 Data = MmioRead32 (Xhc->UsbHostControllerBaseAddress + Xhc->RTSOff + Offset); in XhcPeiReadRuntimeReg()
299 MmioWrite32 (Xhc->UsbHostControllerBaseAddress + Xhc->RTSOff + Offset, Data); in XhcPeiWriteRuntimeReg()
1452 XhcDev->UsbHostControllerBaseAddress = (UINT32) BaseAddress; in XhcPeimEntry()
1468 …(EFI_D_INFO, "XhciPei: UsbHostControllerBaseAddress: %x\n", XhcDev->UsbHostControllerBaseAddress)); in XhcPeimEntry()
|
| /dports/sysutils/uefi-edk2-bhyve-csm/uefi-edk2-aa8d718/MdeModulePkg/Bus/Pci/UhciPei/ |
| H A D | UhcPeim.c | 101 UhcDev->UsbHostControllerBaseAddress = (UINT32) BaseAddress; in UhcPeimEntry()
199 StatusReg = UhcDev->UsbHostControllerBaseAddress + USBSTS; in UhcControlTransfer()
454 CommandContent = USBReadPortW (UhcDev, UhcDev->UsbHostControllerBaseAddress + USBCMD); in UhcBulkTransfer()
457 USBWritePortW (UhcDev, UhcDev->UsbHostControllerBaseAddress + USBCMD, CommandContent); in UhcBulkTransfer()
460 StatusReg = UhcDev->UsbHostControllerBaseAddress + USBSTS; in UhcBulkTransfer()
652 PSAddr = UhcDev->UsbHostControllerBaseAddress + USBPORTSC1 + Index * 2; in UhcGetRootHubPortNumber()
792 PSAddr = UhcDev->UsbHostControllerBaseAddress + USBPORTSC1 + PortNumber * 2; in UhcSetRootHubPortFeature()
793 CommandRegAddr = UhcDev->UsbHostControllerBaseAddress + USBCMD; in UhcSetRootHubPortFeature()
870 PSAddr = UhcDev->UsbHostControllerBaseAddress + USBPORTSC1 + PortNumber * 2; in UhcClearRootHubPortFeature()
976 FrameListBaseAddrReg = UhcDev->UsbHostControllerBaseAddress + USBFLBASEADD; in InitializeUsbHC()
[all …]
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| /dports/emulators/qemu42/qemu-4.2.1/roms/edk2/MdeModulePkg/Bus/Pci/XhciPei/ |
| H A D | XhcPeim.c | 81 Data = MmioRead32 (Xhc->UsbHostControllerBaseAddress + Xhc->CapLength + Offset); in XhcPeiReadOpReg()
102 MmioWrite32 (Xhc->UsbHostControllerBaseAddress + Xhc->CapLength + Offset, Data); in XhcPeiWriteOpReg()
202 Data = MmioRead32 (Xhc->UsbHostControllerBaseAddress + Offset); in XhcPeiReadCapRegister()
226 MmioWrite32 (Xhc->UsbHostControllerBaseAddress + Xhc->DBOff + Offset, Data); in XhcPeiWriteDoorBellReg()
248 Data = MmioRead32 (Xhc->UsbHostControllerBaseAddress + Xhc->RTSOff + Offset); in XhcPeiReadRuntimeReg()
270 MmioWrite32 (Xhc->UsbHostControllerBaseAddress + Xhc->RTSOff + Offset, Data); in XhcPeiWriteRuntimeReg()
1488 XhcDev->UsbHostControllerBaseAddress = (UINT32) BaseAddress; in XhcPeimEntry()
1504 …(EFI_D_INFO, "XhciPei: UsbHostControllerBaseAddress: %x\n", XhcDev->UsbHostControllerBaseAddress)); in XhcPeimEntry()
|
| /dports/emulators/qemu/qemu-6.2.0/roms/edk2/MdeModulePkg/Bus/Pci/XhciPei/ |
| H A D | XhcPeim.c | 81 Data = MmioRead32 (Xhc->UsbHostControllerBaseAddress + Xhc->CapLength + Offset); in XhcPeiReadOpReg()
102 MmioWrite32 (Xhc->UsbHostControllerBaseAddress + Xhc->CapLength + Offset, Data); in XhcPeiWriteOpReg()
202 Data = MmioRead32 (Xhc->UsbHostControllerBaseAddress + Offset); in XhcPeiReadCapRegister()
226 MmioWrite32 (Xhc->UsbHostControllerBaseAddress + Xhc->DBOff + Offset, Data); in XhcPeiWriteDoorBellReg()
248 Data = MmioRead32 (Xhc->UsbHostControllerBaseAddress + Xhc->RTSOff + Offset); in XhcPeiReadRuntimeReg()
270 MmioWrite32 (Xhc->UsbHostControllerBaseAddress + Xhc->RTSOff + Offset, Data); in XhcPeiWriteRuntimeReg()
1488 XhcDev->UsbHostControllerBaseAddress = (UINT32) BaseAddress; in XhcPeimEntry()
1504 …(EFI_D_INFO, "XhciPei: UsbHostControllerBaseAddress: %x\n", XhcDev->UsbHostControllerBaseAddress)); in XhcPeimEntry()
|
| /dports/emulators/qemu5/qemu-5.2.0/roms/edk2/MdeModulePkg/Bus/Pci/XhciPei/ |
| H A D | XhcPeim.c | 81 Data = MmioRead32 (Xhc->UsbHostControllerBaseAddress + Xhc->CapLength + Offset); in XhcPeiReadOpReg()
102 MmioWrite32 (Xhc->UsbHostControllerBaseAddress + Xhc->CapLength + Offset, Data); in XhcPeiWriteOpReg()
202 Data = MmioRead32 (Xhc->UsbHostControllerBaseAddress + Offset); in XhcPeiReadCapRegister()
226 MmioWrite32 (Xhc->UsbHostControllerBaseAddress + Xhc->DBOff + Offset, Data); in XhcPeiWriteDoorBellReg()
248 Data = MmioRead32 (Xhc->UsbHostControllerBaseAddress + Xhc->RTSOff + Offset); in XhcPeiReadRuntimeReg()
270 MmioWrite32 (Xhc->UsbHostControllerBaseAddress + Xhc->RTSOff + Offset, Data); in XhcPeiWriteRuntimeReg()
1488 XhcDev->UsbHostControllerBaseAddress = (UINT32) BaseAddress; in XhcPeimEntry()
1504 …(EFI_D_INFO, "XhciPei: UsbHostControllerBaseAddress: %x\n", XhcDev->UsbHostControllerBaseAddress)); in XhcPeimEntry()
|
| /dports/emulators/qemu60/qemu-6.0.0/roms/edk2/MdeModulePkg/Bus/Pci/XhciPei/ |
| H A D | XhcPeim.c | 81 Data = MmioRead32 (Xhc->UsbHostControllerBaseAddress + Xhc->CapLength + Offset); in XhcPeiReadOpReg()
102 MmioWrite32 (Xhc->UsbHostControllerBaseAddress + Xhc->CapLength + Offset, Data); in XhcPeiWriteOpReg()
202 Data = MmioRead32 (Xhc->UsbHostControllerBaseAddress + Offset); in XhcPeiReadCapRegister()
226 MmioWrite32 (Xhc->UsbHostControllerBaseAddress + Xhc->DBOff + Offset, Data); in XhcPeiWriteDoorBellReg()
248 Data = MmioRead32 (Xhc->UsbHostControllerBaseAddress + Xhc->RTSOff + Offset); in XhcPeiReadRuntimeReg()
270 MmioWrite32 (Xhc->UsbHostControllerBaseAddress + Xhc->RTSOff + Offset, Data); in XhcPeiWriteRuntimeReg()
1488 XhcDev->UsbHostControllerBaseAddress = (UINT32) BaseAddress; in XhcPeimEntry()
1504 …(EFI_D_INFO, "XhciPei: UsbHostControllerBaseAddress: %x\n", XhcDev->UsbHostControllerBaseAddress)); in XhcPeimEntry()
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| /dports/emulators/qemu-utils/qemu-4.2.1/roms/edk2/MdeModulePkg/Bus/Pci/XhciPei/ |
| H A D | XhcPeim.c | 81 Data = MmioRead32 (Xhc->UsbHostControllerBaseAddress + Xhc->CapLength + Offset); in XhcPeiReadOpReg()
102 MmioWrite32 (Xhc->UsbHostControllerBaseAddress + Xhc->CapLength + Offset, Data); in XhcPeiWriteOpReg()
202 Data = MmioRead32 (Xhc->UsbHostControllerBaseAddress + Offset); in XhcPeiReadCapRegister()
226 MmioWrite32 (Xhc->UsbHostControllerBaseAddress + Xhc->DBOff + Offset, Data); in XhcPeiWriteDoorBellReg()
248 Data = MmioRead32 (Xhc->UsbHostControllerBaseAddress + Xhc->RTSOff + Offset); in XhcPeiReadRuntimeReg()
270 MmioWrite32 (Xhc->UsbHostControllerBaseAddress + Xhc->RTSOff + Offset, Data); in XhcPeiWriteRuntimeReg()
1488 XhcDev->UsbHostControllerBaseAddress = (UINT32) BaseAddress; in XhcPeimEntry()
1504 …(EFI_D_INFO, "XhciPei: UsbHostControllerBaseAddress: %x\n", XhcDev->UsbHostControllerBaseAddress)); in XhcPeimEntry()
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| /dports/sysutils/uefi-edk2-qemu/edk2-edk2-stable201911/MdeModulePkg/Bus/Pci/XhciPei/ |
| H A D | XhcPeim.c | 81 Data = MmioRead32 (Xhc->UsbHostControllerBaseAddress + Xhc->CapLength + Offset); in XhcPeiReadOpReg()
102 MmioWrite32 (Xhc->UsbHostControllerBaseAddress + Xhc->CapLength + Offset, Data); in XhcPeiWriteOpReg()
202 Data = MmioRead32 (Xhc->UsbHostControllerBaseAddress + Offset); in XhcPeiReadCapRegister()
226 MmioWrite32 (Xhc->UsbHostControllerBaseAddress + Xhc->DBOff + Offset, Data); in XhcPeiWriteDoorBellReg()
248 Data = MmioRead32 (Xhc->UsbHostControllerBaseAddress + Xhc->RTSOff + Offset); in XhcPeiReadRuntimeReg()
270 MmioWrite32 (Xhc->UsbHostControllerBaseAddress + Xhc->RTSOff + Offset, Data); in XhcPeiWriteRuntimeReg()
1488 XhcDev->UsbHostControllerBaseAddress = (UINT32) BaseAddress; in XhcPeimEntry()
1504 …(EFI_D_INFO, "XhciPei: UsbHostControllerBaseAddress: %x\n", XhcDev->UsbHostControllerBaseAddress)); in XhcPeimEntry()
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| /dports/sysutils/uefi-edk2-bhyve/edk2-edk2-stable202102/MdeModulePkg/Bus/Pci/XhciPei/ |
| H A D | XhcPeim.c | 81 Data = MmioRead32 (Xhc->UsbHostControllerBaseAddress + Xhc->CapLength + Offset); in XhcPeiReadOpReg()
102 MmioWrite32 (Xhc->UsbHostControllerBaseAddress + Xhc->CapLength + Offset, Data); in XhcPeiWriteOpReg()
202 Data = MmioRead32 (Xhc->UsbHostControllerBaseAddress + Offset); in XhcPeiReadCapRegister()
226 MmioWrite32 (Xhc->UsbHostControllerBaseAddress + Xhc->DBOff + Offset, Data); in XhcPeiWriteDoorBellReg()
248 Data = MmioRead32 (Xhc->UsbHostControllerBaseAddress + Xhc->RTSOff + Offset); in XhcPeiReadRuntimeReg()
270 MmioWrite32 (Xhc->UsbHostControllerBaseAddress + Xhc->RTSOff + Offset, Data); in XhcPeiWriteRuntimeReg()
1488 XhcDev->UsbHostControllerBaseAddress = (UINT32) BaseAddress; in XhcPeimEntry()
1504 …(EFI_D_INFO, "XhciPei: UsbHostControllerBaseAddress: %x\n", XhcDev->UsbHostControllerBaseAddress)); in XhcPeimEntry()
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| /dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/edk2/MdeModulePkg/Bus/Pci/XhciPei/ |
| H A D | XhcPeim.c | 81 Data = MmioRead32 (Xhc->UsbHostControllerBaseAddress + Xhc->CapLength + Offset); in XhcPeiReadOpReg()
102 MmioWrite32 (Xhc->UsbHostControllerBaseAddress + Xhc->CapLength + Offset, Data); in XhcPeiWriteOpReg()
202 Data = MmioRead32 (Xhc->UsbHostControllerBaseAddress + Offset); in XhcPeiReadCapRegister()
226 MmioWrite32 (Xhc->UsbHostControllerBaseAddress + Xhc->DBOff + Offset, Data); in XhcPeiWriteDoorBellReg()
248 Data = MmioRead32 (Xhc->UsbHostControllerBaseAddress + Xhc->RTSOff + Offset); in XhcPeiReadRuntimeReg()
270 MmioWrite32 (Xhc->UsbHostControllerBaseAddress + Xhc->RTSOff + Offset, Data); in XhcPeiWriteRuntimeReg()
1488 XhcDev->UsbHostControllerBaseAddress = (UINT32) BaseAddress; in XhcPeimEntry()
1504 …(EFI_D_INFO, "XhciPei: UsbHostControllerBaseAddress: %x\n", XhcDev->UsbHostControllerBaseAddress)); in XhcPeimEntry()
|
| /dports/sysutils/edk2/edk2-edk2-stable202102/MdeModulePkg/Bus/Pci/XhciPei/ |
| H A D | XhcPeim.c | 81 Data = MmioRead32 (Xhc->UsbHostControllerBaseAddress + Xhc->CapLength + Offset); in XhcPeiReadOpReg()
102 MmioWrite32 (Xhc->UsbHostControllerBaseAddress + Xhc->CapLength + Offset, Data); in XhcPeiWriteOpReg()
202 Data = MmioRead32 (Xhc->UsbHostControllerBaseAddress + Offset); in XhcPeiReadCapRegister()
226 MmioWrite32 (Xhc->UsbHostControllerBaseAddress + Xhc->DBOff + Offset, Data); in XhcPeiWriteDoorBellReg()
248 Data = MmioRead32 (Xhc->UsbHostControllerBaseAddress + Xhc->RTSOff + Offset); in XhcPeiReadRuntimeReg()
270 MmioWrite32 (Xhc->UsbHostControllerBaseAddress + Xhc->RTSOff + Offset, Data); in XhcPeiWriteRuntimeReg()
1488 XhcDev->UsbHostControllerBaseAddress = (UINT32) BaseAddress; in XhcPeimEntry()
1504 …(EFI_D_INFO, "XhciPei: UsbHostControllerBaseAddress: %x\n", XhcDev->UsbHostControllerBaseAddress)); in XhcPeimEntry()
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| /dports/emulators/qemu60/qemu-6.0.0/roms/edk2/MdeModulePkg/Bus/Pci/EhciPei/ |
| H A D | EhcPeim.c | 52 Data = MmioRead32 (Ehc->UsbHostControllerBaseAddress + Ehc->CapLen + Offset); in EhcReadOpReg()
75 MmioWrite32(Ehc->UsbHostControllerBaseAddress + Ehc->CapLen + Offset, Data); in EhcWriteOpReg()
176 Data = MmioRead32(Ehc->UsbHostControllerBaseAddress + Offset); in EhcReadCapRegister()
1247 EhcDev->UsbHostControllerBaseAddress = (UINT32) BaseAddress; in EhcPeimEntry()
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| /dports/sysutils/uefi-edk2-bhyve/edk2-edk2-stable202102/MdeModulePkg/Bus/Pci/EhciPei/ |
| H A D | EhcPeim.c | 52 Data = MmioRead32 (Ehc->UsbHostControllerBaseAddress + Ehc->CapLen + Offset); in EhcReadOpReg()
75 MmioWrite32(Ehc->UsbHostControllerBaseAddress + Ehc->CapLen + Offset, Data); in EhcWriteOpReg()
176 Data = MmioRead32(Ehc->UsbHostControllerBaseAddress + Offset); in EhcReadCapRegister()
1247 EhcDev->UsbHostControllerBaseAddress = (UINT32) BaseAddress; in EhcPeimEntry()
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| /dports/sysutils/uefi-edk2-bhyve-csm/uefi-edk2-aa8d718/MdeModulePkg/Bus/Pci/EhciPei/ |
| H A D | EhcPeim.c | 59 Data = MmioRead32 (Ehc->UsbHostControllerBaseAddress + Ehc->CapLen + Offset); in EhcReadOpReg()
82 MmioWrite32(Ehc->UsbHostControllerBaseAddress + Ehc->CapLen + Offset, Data); in EhcWriteOpReg()
183 Data = MmioRead32(Ehc->UsbHostControllerBaseAddress + Offset); in EhcReadCapRegister()
1214 EhcDev->UsbHostControllerBaseAddress = (UINT32) BaseAddress; in EhcPeimEntry()
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| /dports/emulators/qemu42/qemu-4.2.1/roms/edk2/MdeModulePkg/Bus/Pci/EhciPei/ |
| H A D | EhcPeim.c | 52 Data = MmioRead32 (Ehc->UsbHostControllerBaseAddress + Ehc->CapLen + Offset); in EhcReadOpReg()
75 MmioWrite32(Ehc->UsbHostControllerBaseAddress + Ehc->CapLen + Offset, Data); in EhcWriteOpReg()
176 Data = MmioRead32(Ehc->UsbHostControllerBaseAddress + Offset); in EhcReadCapRegister()
1247 EhcDev->UsbHostControllerBaseAddress = (UINT32) BaseAddress; in EhcPeimEntry()
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| /dports/emulators/qemu/qemu-6.2.0/roms/edk2/MdeModulePkg/Bus/Pci/EhciPei/ |
| H A D | EhcPeim.c | 52 Data = MmioRead32 (Ehc->UsbHostControllerBaseAddress + Ehc->CapLen + Offset); in EhcReadOpReg()
75 MmioWrite32(Ehc->UsbHostControllerBaseAddress + Ehc->CapLen + Offset, Data); in EhcWriteOpReg()
176 Data = MmioRead32(Ehc->UsbHostControllerBaseAddress + Offset); in EhcReadCapRegister()
1247 EhcDev->UsbHostControllerBaseAddress = (UINT32) BaseAddress; in EhcPeimEntry()
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