| /dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/drivers/video/meson/ |
| H A D | meson_vclk.c | 41 #define VCLK2_SEL_SHIFT 16 macro
280 VCLK2_SEL_MASK, (0 << VCLK2_SEL_SHIFT)); in meson_venci_cvbs_clock_config()
283 VCLK2_SEL_MASK, (4 << VCLK2_SEL_SHIFT)); in meson_venci_cvbs_clock_config()
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| /dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/drivers/video/meson/ |
| H A D | meson_vclk.c | 41 #define VCLK2_SEL_SHIFT 16 macro
280 VCLK2_SEL_MASK, (0 << VCLK2_SEL_SHIFT)); in meson_venci_cvbs_clock_config()
283 VCLK2_SEL_MASK, (4 << VCLK2_SEL_SHIFT)); in meson_venci_cvbs_clock_config()
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| /dports/sysutils/u-boot-wandboard/u-boot-2021.07/drivers/video/meson/ |
| H A D | meson_vclk.c | 41 #define VCLK2_SEL_SHIFT 16 macro
280 VCLK2_SEL_MASK, (0 << VCLK2_SEL_SHIFT)); in meson_venci_cvbs_clock_config()
283 VCLK2_SEL_MASK, (4 << VCLK2_SEL_SHIFT)); in meson_venci_cvbs_clock_config()
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| /dports/sysutils/u-boot-chip/u-boot-2021.07/drivers/video/meson/ |
| H A D | meson_vclk.c | 41 #define VCLK2_SEL_SHIFT 16 macro
280 VCLK2_SEL_MASK, (0 << VCLK2_SEL_SHIFT)); in meson_venci_cvbs_clock_config()
283 VCLK2_SEL_MASK, (4 << VCLK2_SEL_SHIFT)); in meson_venci_cvbs_clock_config()
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| /dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/drivers/video/meson/ |
| H A D | meson_vclk.c | 41 #define VCLK2_SEL_SHIFT 16 macro
280 VCLK2_SEL_MASK, (0 << VCLK2_SEL_SHIFT)); in meson_venci_cvbs_clock_config()
283 VCLK2_SEL_MASK, (4 << VCLK2_SEL_SHIFT)); in meson_venci_cvbs_clock_config()
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| /dports/sysutils/u-boot-firefly-rk3399/u-boot-2021.07/drivers/video/meson/ |
| H A D | meson_vclk.c | 41 #define VCLK2_SEL_SHIFT 16 macro
280 VCLK2_SEL_MASK, (0 << VCLK2_SEL_SHIFT)); in meson_venci_cvbs_clock_config()
283 VCLK2_SEL_MASK, (4 << VCLK2_SEL_SHIFT)); in meson_venci_cvbs_clock_config()
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| /dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/drivers/video/meson/ |
| H A D | meson_vclk.c | 41 #define VCLK2_SEL_SHIFT 16 macro
280 VCLK2_SEL_MASK, (0 << VCLK2_SEL_SHIFT)); in meson_venci_cvbs_clock_config()
283 VCLK2_SEL_MASK, (4 << VCLK2_SEL_SHIFT)); in meson_venci_cvbs_clock_config()
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| /dports/sysutils/u-boot-a13-olinuxino/u-boot-2021.07/drivers/video/meson/ |
| H A D | meson_vclk.c | 41 #define VCLK2_SEL_SHIFT 16 macro
280 VCLK2_SEL_MASK, (0 << VCLK2_SEL_SHIFT)); in meson_venci_cvbs_clock_config()
283 VCLK2_SEL_MASK, (4 << VCLK2_SEL_SHIFT)); in meson_venci_cvbs_clock_config()
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| /dports/sysutils/u-boot-sinovoip-bpi-m3/u-boot-2021.07/drivers/video/meson/ |
| H A D | meson_vclk.c | 41 #define VCLK2_SEL_SHIFT 16 macro
280 VCLK2_SEL_MASK, (0 << VCLK2_SEL_SHIFT)); in meson_venci_cvbs_clock_config()
283 VCLK2_SEL_MASK, (4 << VCLK2_SEL_SHIFT)); in meson_venci_cvbs_clock_config()
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| /dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/drivers/video/meson/ |
| H A D | meson_vclk.c | 41 #define VCLK2_SEL_SHIFT 16 macro
280 VCLK2_SEL_MASK, (0 << VCLK2_SEL_SHIFT)); in meson_venci_cvbs_clock_config()
283 VCLK2_SEL_MASK, (4 << VCLK2_SEL_SHIFT)); in meson_venci_cvbs_clock_config()
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| /dports/sysutils/u-boot-sopine/u-boot-2021.07/drivers/video/meson/ |
| H A D | meson_vclk.c | 41 #define VCLK2_SEL_SHIFT 16 macro
280 VCLK2_SEL_MASK, (0 << VCLK2_SEL_SHIFT)); in meson_venci_cvbs_clock_config()
283 VCLK2_SEL_MASK, (4 << VCLK2_SEL_SHIFT)); in meson_venci_cvbs_clock_config()
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| /dports/sysutils/u-boot-rpi/u-boot-2021.07/drivers/video/meson/ |
| H A D | meson_vclk.c | 41 #define VCLK2_SEL_SHIFT 16 macro
280 VCLK2_SEL_MASK, (0 << VCLK2_SEL_SHIFT)); in meson_venci_cvbs_clock_config()
283 VCLK2_SEL_MASK, (4 << VCLK2_SEL_SHIFT)); in meson_venci_cvbs_clock_config()
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| /dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/drivers/video/meson/ |
| H A D | meson_vclk.c | 41 #define VCLK2_SEL_SHIFT 16 macro
280 VCLK2_SEL_MASK, (0 << VCLK2_SEL_SHIFT)); in meson_venci_cvbs_clock_config()
283 VCLK2_SEL_MASK, (4 << VCLK2_SEL_SHIFT)); in meson_venci_cvbs_clock_config()
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| /dports/sysutils/u-boot-nanopi-neo2/u-boot-2021.07/drivers/video/meson/ |
| H A D | meson_vclk.c | 41 #define VCLK2_SEL_SHIFT 16 macro
280 VCLK2_SEL_MASK, (0 << VCLK2_SEL_SHIFT)); in meson_venci_cvbs_clock_config()
283 VCLK2_SEL_MASK, (4 << VCLK2_SEL_SHIFT)); in meson_venci_cvbs_clock_config()
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| /dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/drivers/video/meson/ |
| H A D | meson_vclk.c | 41 #define VCLK2_SEL_SHIFT 16 macro
280 VCLK2_SEL_MASK, (0 << VCLK2_SEL_SHIFT)); in meson_venci_cvbs_clock_config()
283 VCLK2_SEL_MASK, (4 << VCLK2_SEL_SHIFT)); in meson_venci_cvbs_clock_config()
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| /dports/sysutils/u-boot-nanopi-m1plus/u-boot-2021.07/drivers/video/meson/ |
| H A D | meson_vclk.c | 41 #define VCLK2_SEL_SHIFT 16 macro
280 VCLK2_SEL_MASK, (0 << VCLK2_SEL_SHIFT)); in meson_venci_cvbs_clock_config()
283 VCLK2_SEL_MASK, (4 << VCLK2_SEL_SHIFT)); in meson_venci_cvbs_clock_config()
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| /dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/drivers/video/meson/ |
| H A D | meson_vclk.c | 41 #define VCLK2_SEL_SHIFT 16 macro
280 VCLK2_SEL_MASK, (0 << VCLK2_SEL_SHIFT)); in meson_venci_cvbs_clock_config()
283 VCLK2_SEL_MASK, (4 << VCLK2_SEL_SHIFT)); in meson_venci_cvbs_clock_config()
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| /dports/sysutils/u-boot-clearfog/u-boot-2021.07/drivers/video/meson/ |
| H A D | meson_vclk.c | 41 #define VCLK2_SEL_SHIFT 16 macro
280 VCLK2_SEL_MASK, (0 << VCLK2_SEL_SHIFT)); in meson_venci_cvbs_clock_config()
283 VCLK2_SEL_MASK, (4 << VCLK2_SEL_SHIFT)); in meson_venci_cvbs_clock_config()
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| /dports/sysutils/u-boot-cubieboard/u-boot-2021.07/drivers/video/meson/ |
| H A D | meson_vclk.c | 41 #define VCLK2_SEL_SHIFT 16 macro
280 VCLK2_SEL_MASK, (0 << VCLK2_SEL_SHIFT)); in meson_venci_cvbs_clock_config()
283 VCLK2_SEL_MASK, (4 << VCLK2_SEL_SHIFT)); in meson_venci_cvbs_clock_config()
|
| /dports/sysutils/u-boot-orangepi-zero-plus/u-boot-2021.07/drivers/video/meson/ |
| H A D | meson_vclk.c | 41 #define VCLK2_SEL_SHIFT 16 macro
280 VCLK2_SEL_MASK, (0 << VCLK2_SEL_SHIFT)); in meson_venci_cvbs_clock_config()
283 VCLK2_SEL_MASK, (4 << VCLK2_SEL_SHIFT)); in meson_venci_cvbs_clock_config()
|
| /dports/sysutils/u-boot-orangepi-r1/u-boot-2021.07/drivers/video/meson/ |
| H A D | meson_vclk.c | 41 #define VCLK2_SEL_SHIFT 16 macro
280 VCLK2_SEL_MASK, (0 << VCLK2_SEL_SHIFT)); in meson_venci_cvbs_clock_config()
283 VCLK2_SEL_MASK, (4 << VCLK2_SEL_SHIFT)); in meson_venci_cvbs_clock_config()
|
| /dports/sysutils/u-boot-orangepi-zero/u-boot-2021.07/drivers/video/meson/ |
| H A D | meson_vclk.c | 41 #define VCLK2_SEL_SHIFT 16 macro
280 VCLK2_SEL_MASK, (0 << VCLK2_SEL_SHIFT)); in meson_venci_cvbs_clock_config()
283 VCLK2_SEL_MASK, (4 << VCLK2_SEL_SHIFT)); in meson_venci_cvbs_clock_config()
|
| /dports/sysutils/u-boot-pandaboard/u-boot-2021.07/drivers/video/meson/ |
| H A D | meson_vclk.c | 41 #define VCLK2_SEL_SHIFT 16 macro
280 VCLK2_SEL_MASK, (0 << VCLK2_SEL_SHIFT)); in meson_venci_cvbs_clock_config()
283 VCLK2_SEL_MASK, (4 << VCLK2_SEL_SHIFT)); in meson_venci_cvbs_clock_config()
|
| /dports/sysutils/u-boot-pine64/u-boot-2021.07/drivers/video/meson/ |
| H A D | meson_vclk.c | 41 #define VCLK2_SEL_SHIFT 16 macro
280 VCLK2_SEL_MASK, (0 << VCLK2_SEL_SHIFT)); in meson_venci_cvbs_clock_config()
283 VCLK2_SEL_MASK, (4 << VCLK2_SEL_SHIFT)); in meson_venci_cvbs_clock_config()
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| /dports/sysutils/u-boot-pine-h64/u-boot-2021.07/drivers/video/meson/ |
| H A D | meson_vclk.c | 41 #define VCLK2_SEL_SHIFT 16 macro
280 VCLK2_SEL_MASK, (0 << VCLK2_SEL_SHIFT)); in meson_venci_cvbs_clock_config()
283 VCLK2_SEL_MASK, (4 << VCLK2_SEL_SHIFT)); in meson_venci_cvbs_clock_config()
|