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Searched refs:VCO_MIN_HZ (Results 1 – 25 of 543) sorted by relevance

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/dports/sysutils/u-boot-chip/u-boot-2021.07/drivers/clk/rockchip/
H A Dclk_rk3128.c26 VCO_MIN_HZ = 600 * 1000000, enumerator
55 assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ && in rkclk_set_pll()
96 postdiv1 = DIV_ROUND_UP(VCO_MIN_HZ / 1000, freq_khz); in pll_para_config()
104 if (vco_khz < (VCO_MIN_HZ / 1000) || vco_khz > (VCO_MAX_HZ / 1000) || in pll_para_config()
/dports/emulators/qemu42/qemu-4.2.1/roms/u-boot/drivers/clk/rockchip/
H A Dclk_rk3128.c22 VCO_MIN_HZ = 600 * 1000000, enumerator
51 assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ && in rkclk_set_pll()
92 postdiv1 = DIV_ROUND_UP(VCO_MIN_HZ / 1000, freq_khz); in pll_para_config()
100 if (vco_khz < (VCO_MIN_HZ / 1000) || vco_khz > (VCO_MAX_HZ / 1000) || in pll_para_config()
/dports/emulators/qemu5/qemu-5.2.0/roms/u-boot/drivers/clk/rockchip/
H A Dclk_rk3128.c22 VCO_MIN_HZ = 600 * 1000000, enumerator
51 assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ && in rkclk_set_pll()
92 postdiv1 = DIV_ROUND_UP(VCO_MIN_HZ / 1000, freq_khz); in pll_para_config()
100 if (vco_khz < (VCO_MIN_HZ / 1000) || vco_khz > (VCO_MAX_HZ / 1000) || in pll_para_config()
/dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/drivers/clk/rockchip/
H A Dclk_rk3128.c26 VCO_MIN_HZ = 600 * 1000000, enumerator
55 assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ && in rkclk_set_pll()
96 postdiv1 = DIV_ROUND_UP(VCO_MIN_HZ / 1000, freq_khz); in pll_para_config()
104 if (vco_khz < (VCO_MIN_HZ / 1000) || vco_khz > (VCO_MAX_HZ / 1000) || in pll_para_config()
/dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/drivers/clk/rockchip/
H A Dclk_rk3128.c26 VCO_MIN_HZ = 600 * 1000000, enumerator
55 assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ && in rkclk_set_pll()
96 postdiv1 = DIV_ROUND_UP(VCO_MIN_HZ / 1000, freq_khz); in pll_para_config()
104 if (vco_khz < (VCO_MIN_HZ / 1000) || vco_khz > (VCO_MAX_HZ / 1000) || in pll_para_config()
/dports/sysutils/u-boot-olinuxino-lime2-emmc/u-boot-2021.07/drivers/clk/rockchip/
H A Dclk_rk3128.c26 VCO_MIN_HZ = 600 * 1000000, enumerator
55 assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ && in rkclk_set_pll()
96 postdiv1 = DIV_ROUND_UP(VCO_MIN_HZ / 1000, freq_khz); in pll_para_config()
104 if (vco_khz < (VCO_MIN_HZ / 1000) || vco_khz > (VCO_MAX_HZ / 1000) || in pll_para_config()
/dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/drivers/clk/rockchip/
H A Dclk_rk3128.c26 VCO_MIN_HZ = 600 * 1000000, enumerator
55 assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ && in rkclk_set_pll()
96 postdiv1 = DIV_ROUND_UP(VCO_MIN_HZ / 1000, freq_khz); in pll_para_config()
104 if (vco_khz < (VCO_MIN_HZ / 1000) || vco_khz > (VCO_MAX_HZ / 1000) || in pll_para_config()
/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot/drivers/clk/rockchip/
H A Dclk_rk3128.c22 VCO_MIN_HZ = 600 * 1000000, enumerator
51 assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ && in rkclk_set_pll()
92 postdiv1 = DIV_ROUND_UP(VCO_MIN_HZ / 1000, freq_khz); in pll_para_config()
100 if (vco_khz < (VCO_MIN_HZ / 1000) || vco_khz > (VCO_MAX_HZ / 1000) || in pll_para_config()
/dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/drivers/clk/rockchip/
H A Dclk_rk3128.c26 VCO_MIN_HZ = 600 * 1000000, enumerator
55 assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ && in rkclk_set_pll()
96 postdiv1 = DIV_ROUND_UP(VCO_MIN_HZ / 1000, freq_khz); in pll_para_config()
104 if (vco_khz < (VCO_MIN_HZ / 1000) || vco_khz > (VCO_MAX_HZ / 1000) || in pll_para_config()
/dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/drivers/clk/rockchip/
H A Dclk_rk3128.c26 VCO_MIN_HZ = 600 * 1000000, enumerator
55 assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ && in rkclk_set_pll()
96 postdiv1 = DIV_ROUND_UP(VCO_MIN_HZ / 1000, freq_khz); in pll_para_config()
104 if (vco_khz < (VCO_MIN_HZ / 1000) || vco_khz > (VCO_MAX_HZ / 1000) || in pll_para_config()
/dports/sysutils/u-boot-cubieboard/u-boot-2021.07/drivers/clk/rockchip/
H A Dclk_rk3128.c26 VCO_MIN_HZ = 600 * 1000000, enumerator
55 assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ && in rkclk_set_pll()
96 postdiv1 = DIV_ROUND_UP(VCO_MIN_HZ / 1000, freq_khz); in pll_para_config()
104 if (vco_khz < (VCO_MIN_HZ / 1000) || vco_khz > (VCO_MAX_HZ / 1000) || in pll_para_config()
/dports/sysutils/u-boot-firefly-rk3399/u-boot-2021.07/drivers/clk/rockchip/
H A Dclk_rk3128.c26 VCO_MIN_HZ = 600 * 1000000, enumerator
55 assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ && in rkclk_set_pll()
96 postdiv1 = DIV_ROUND_UP(VCO_MIN_HZ / 1000, freq_khz); in pll_para_config()
104 if (vco_khz < (VCO_MIN_HZ / 1000) || vco_khz > (VCO_MAX_HZ / 1000) || in pll_para_config()
/dports/sysutils/u-boot-sinovoip-bpi-m3/u-boot-2021.07/drivers/clk/rockchip/
H A Dclk_rk3128.c26 VCO_MIN_HZ = 600 * 1000000, enumerator
55 assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ && in rkclk_set_pll()
96 postdiv1 = DIV_ROUND_UP(VCO_MIN_HZ / 1000, freq_khz); in pll_para_config()
104 if (vco_khz < (VCO_MIN_HZ / 1000) || vco_khz > (VCO_MAX_HZ / 1000) || in pll_para_config()
/dports/sysutils/u-boot-a13-olinuxino/u-boot-2021.07/drivers/clk/rockchip/
H A Dclk_rk3128.c26 VCO_MIN_HZ = 600 * 1000000, enumerator
55 assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ && in rkclk_set_pll()
96 postdiv1 = DIV_ROUND_UP(VCO_MIN_HZ / 1000, freq_khz); in pll_para_config()
104 if (vco_khz < (VCO_MIN_HZ / 1000) || vco_khz > (VCO_MAX_HZ / 1000) || in pll_para_config()
/dports/sysutils/u-boot-sopine/u-boot-2021.07/drivers/clk/rockchip/
H A Dclk_rk3128.c26 VCO_MIN_HZ = 600 * 1000000, enumerator
55 assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ && in rkclk_set_pll()
96 postdiv1 = DIV_ROUND_UP(VCO_MIN_HZ / 1000, freq_khz); in pll_para_config()
104 if (vco_khz < (VCO_MIN_HZ / 1000) || vco_khz > (VCO_MAX_HZ / 1000) || in pll_para_config()
/dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/drivers/clk/rockchip/
H A Dclk_rk3128.c26 VCO_MIN_HZ = 600 * 1000000, enumerator
55 assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ && in rkclk_set_pll()
96 postdiv1 = DIV_ROUND_UP(VCO_MIN_HZ / 1000, freq_khz); in pll_para_config()
104 if (vco_khz < (VCO_MIN_HZ / 1000) || vco_khz > (VCO_MAX_HZ / 1000) || in pll_para_config()
/dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/drivers/clk/rockchip/
H A Dclk_rk3128.c26 VCO_MIN_HZ = 600 * 1000000, enumerator
55 assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ && in rkclk_set_pll()
96 postdiv1 = DIV_ROUND_UP(VCO_MIN_HZ / 1000, freq_khz); in pll_para_config()
104 if (vco_khz < (VCO_MIN_HZ / 1000) || vco_khz > (VCO_MAX_HZ / 1000) || in pll_para_config()
/dports/sysutils/u-boot-rpi/u-boot-2021.07/drivers/clk/rockchip/
H A Dclk_rk3128.c26 VCO_MIN_HZ = 600 * 1000000, enumerator
55 assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ && in rkclk_set_pll()
96 postdiv1 = DIV_ROUND_UP(VCO_MIN_HZ / 1000, freq_khz); in pll_para_config()
104 if (vco_khz < (VCO_MIN_HZ / 1000) || vco_khz > (VCO_MAX_HZ / 1000) || in pll_para_config()
/dports/sysutils/u-boot-nanopi-neo/u-boot-2021.07/drivers/clk/rockchip/
H A Dclk_rk3128.c26 VCO_MIN_HZ = 600 * 1000000, enumerator
55 assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ && in rkclk_set_pll()
96 postdiv1 = DIV_ROUND_UP(VCO_MIN_HZ / 1000, freq_khz); in pll_para_config()
104 if (vco_khz < (VCO_MIN_HZ / 1000) || vco_khz > (VCO_MAX_HZ / 1000) || in pll_para_config()
/dports/sysutils/u-boot-nanopi-m1plus/u-boot-2021.07/drivers/clk/rockchip/
H A Dclk_rk3128.c26 VCO_MIN_HZ = 600 * 1000000, enumerator
55 assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ && in rkclk_set_pll()
96 postdiv1 = DIV_ROUND_UP(VCO_MIN_HZ / 1000, freq_khz); in pll_para_config()
104 if (vco_khz < (VCO_MIN_HZ / 1000) || vco_khz > (VCO_MAX_HZ / 1000) || in pll_para_config()
/dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/drivers/clk/rockchip/
H A Dclk_rk3128.c26 VCO_MIN_HZ = 600 * 1000000, enumerator
55 assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ && in rkclk_set_pll()
96 postdiv1 = DIV_ROUND_UP(VCO_MIN_HZ / 1000, freq_khz); in pll_para_config()
104 if (vco_khz < (VCO_MIN_HZ / 1000) || vco_khz > (VCO_MAX_HZ / 1000) || in pll_para_config()
/dports/sysutils/u-boot-nanopi-neo-air/u-boot-2021.07/drivers/clk/rockchip/
H A Dclk_rk3128.c26 VCO_MIN_HZ = 600 * 1000000, enumerator
55 assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ && in rkclk_set_pll()
96 postdiv1 = DIV_ROUND_UP(VCO_MIN_HZ / 1000, freq_khz); in pll_para_config()
104 if (vco_khz < (VCO_MIN_HZ / 1000) || vco_khz > (VCO_MAX_HZ / 1000) || in pll_para_config()
/dports/sysutils/u-boot-beaglebone/u-boot-2021.07/drivers/clk/rockchip/
H A Dclk_rk3128.c26 VCO_MIN_HZ = 600 * 1000000, enumerator
55 assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ && in rkclk_set_pll()
96 postdiv1 = DIV_ROUND_UP(VCO_MIN_HZ / 1000, freq_khz); in pll_para_config()
104 if (vco_khz < (VCO_MIN_HZ / 1000) || vco_khz > (VCO_MAX_HZ / 1000) || in pll_para_config()
/dports/sysutils/u-boot-wandboard/u-boot-2021.07/drivers/clk/rockchip/
H A Dclk_rk3128.c26 VCO_MIN_HZ = 600 * 1000000, enumerator
55 assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ && in rkclk_set_pll()
96 postdiv1 = DIV_ROUND_UP(VCO_MIN_HZ / 1000, freq_khz); in pll_para_config()
104 if (vco_khz < (VCO_MIN_HZ / 1000) || vco_khz > (VCO_MAX_HZ / 1000) || in pll_para_config()
/dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot/drivers/clk/rockchip/
H A Dclk_rk3128.c22 VCO_MIN_HZ = 600 * 1000000, enumerator
51 assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ && in rkclk_set_pll()
92 postdiv1 = DIV_ROUND_UP(VCO_MIN_HZ / 1000, freq_khz); in pll_para_config()
100 if (vco_khz < (VCO_MIN_HZ / 1000) || vco_khz > (VCO_MAX_HZ / 1000) || in pll_para_config()

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