| /dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUInstCombineIntrinsic.cpp | 750 Value *VDstIn = II.getArgOperand(0); in instCombineIntrinsic() local
751 if (isa<UndefValue>(VDstIn)) in instCombineIntrinsic()
759 return IC.replaceOperand(II, 0, UndefValue::get(VDstIn->getType())); in instCombineIntrinsic()
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| H A D | AMDGPUInstructionSelector.cpp | 817 Register VDstIn = MI.getOperand(4).getReg(); in selectWritelane() local
853 MIB.addReg(VDstIn); in selectWritelane()
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| /dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUInstCombineIntrinsic.cpp | 754 Value *VDstIn = II.getArgOperand(0); in instCombineIntrinsic() local
755 if (isa<UndefValue>(VDstIn)) in instCombineIntrinsic()
763 return IC.replaceOperand(II, 0, UndefValue::get(VDstIn->getType())); in instCombineIntrinsic()
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| H A D | AMDGPUInstructionSelector.cpp | 842 Register VDstIn = MI.getOperand(4).getReg(); in selectWritelane() local
878 MIB.addReg(VDstIn); in selectWritelane()
|
| /dports/graphics/llvm-mesa/llvm-13.0.1.src/lib/Target/AMDGPU/ |
| H A D | AMDGPUInstCombineIntrinsic.cpp | 754 Value *VDstIn = II.getArgOperand(0); in instCombineIntrinsic() local
755 if (isa<UndefValue>(VDstIn)) in instCombineIntrinsic()
763 return IC.replaceOperand(II, 0, UndefValue::get(VDstIn->getType())); in instCombineIntrinsic()
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| H A D | AMDGPUInstructionSelector.cpp | 842 Register VDstIn = MI.getOperand(4).getReg(); in selectWritelane() local
878 MIB.addReg(VDstIn); in selectWritelane()
|
| /dports/devel/llvm12/llvm-project-12.0.1.src/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUInstCombineIntrinsic.cpp | 754 Value *VDstIn = II.getArgOperand(0); in instCombineIntrinsic() local
755 if (isa<UndefValue>(VDstIn)) in instCombineIntrinsic()
763 return IC.replaceOperand(II, 0, UndefValue::get(VDstIn->getType())); in instCombineIntrinsic()
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| H A D | AMDGPUInstructionSelector.cpp | 806 Register VDstIn = MI.getOperand(4).getReg(); in selectWritelane() local
842 MIB.addReg(VDstIn); in selectWritelane()
|
| /dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUInstCombineIntrinsic.cpp | 754 Value *VDstIn = II.getArgOperand(0); in instCombineIntrinsic() local
755 if (isa<UndefValue>(VDstIn)) in instCombineIntrinsic()
763 return IC.replaceOperand(II, 0, UndefValue::get(VDstIn->getType())); in instCombineIntrinsic()
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| H A D | AMDGPUInstructionSelector.cpp | 842 Register VDstIn = MI.getOperand(4).getReg(); in selectWritelane() local
878 MIB.addReg(VDstIn); in selectWritelane()
|
| /dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUInstCombineIntrinsic.cpp | 751 Value *VDstIn = II.getArgOperand(0); in instCombineIntrinsic() local
752 if (isa<UndefValue>(VDstIn)) in instCombineIntrinsic()
760 return IC.replaceOperand(II, 0, UndefValue::get(VDstIn->getType())); in instCombineIntrinsic()
|
| H A D | AMDGPUInstructionSelector.cpp | 842 Register VDstIn = MI.getOperand(4).getReg(); in selectWritelane() local
878 MIB.addReg(VDstIn); in selectWritelane()
|
| /dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUInstCombineIntrinsic.cpp | 754 Value *VDstIn = II.getArgOperand(0); in instCombineIntrinsic() local
755 if (isa<UndefValue>(VDstIn)) in instCombineIntrinsic()
763 return IC.replaceOperand(II, 0, UndefValue::get(VDstIn->getType())); in instCombineIntrinsic()
|
| H A D | AMDGPUInstructionSelector.cpp | 842 Register VDstIn = MI.getOperand(4).getReg(); in selectWritelane() local
878 MIB.addReg(VDstIn); in selectWritelane()
|
| /dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUInstCombineIntrinsic.cpp | 754 Value *VDstIn = II.getArgOperand(0); in instCombineIntrinsic() local
755 if (isa<UndefValue>(VDstIn)) in instCombineIntrinsic()
763 return IC.replaceOperand(II, 0, UndefValue::get(VDstIn->getType())); in instCombineIntrinsic()
|
| H A D | AMDGPUInstructionSelector.cpp | 806 Register VDstIn = MI.getOperand(4).getReg(); in selectWritelane() local
842 MIB.addReg(VDstIn); in selectWritelane()
|
| /dports/devel/llvm13/llvm-project-13.0.1.src/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUInstCombineIntrinsic.cpp | 754 Value *VDstIn = II.getArgOperand(0); in instCombineIntrinsic() local
755 if (isa<UndefValue>(VDstIn)) in instCombineIntrinsic()
763 return IC.replaceOperand(II, 0, UndefValue::get(VDstIn->getType())); in instCombineIntrinsic()
|
| H A D | AMDGPUInstructionSelector.cpp | 842 Register VDstIn = MI.getOperand(4).getReg(); in selectWritelane() local
878 MIB.addReg(VDstIn); in selectWritelane()
|
| /dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineCalls.cpp | 4350 Value *VDstIn = II->getArgOperand(0); in visitCallInst() local
4351 if (isa<UndefValue>(VDstIn)) in visitCallInst()
4359 return replaceOperand(*II, 0, UndefValue::get(VDstIn->getType())); in visitCallInst()
|
| /dports/devel/llvm11/llvm-11.0.1.src/lib/Transforms/InstCombine/ |
| H A D | InstCombineCalls.cpp | 4051 Value *VDstIn = II->getArgOperand(0); in visitCallInst() local
4052 if (isa<UndefValue>(VDstIn)) in visitCallInst()
4060 return replaceOperand(*II, 0, UndefValue::get(VDstIn->getType())); in visitCallInst()
|
| /dports/devel/llvm90/llvm-9.0.1.src/lib/Target/AMDGPU/ |
| H A D | SIISelLowering.cpp | 10177 SDValue VDstIn = Node->getOperand(6); in PostISelFolding() local
10178 if (VDstIn.isMachineOpcode() in PostISelFolding()
10179 && VDstIn.getMachineOpcode() == AMDGPU::IMPLICIT_DEF) in PostISelFolding()
|
| /dports/devel/llvm10/llvm-10.0.1.src/lib/Target/AMDGPU/ |
| H A D | SIISelLowering.cpp | 10415 SDValue VDstIn = Node->getOperand(6); in PostISelFolding() local
10416 if (VDstIn.isMachineOpcode() in PostISelFolding()
10417 && VDstIn.getMachineOpcode() == AMDGPU::IMPLICIT_DEF) in PostISelFolding()
|
| /dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| H A D | SIISelLowering.cpp | 10415 SDValue VDstIn = Node->getOperand(6); in PostISelFolding() local
10416 if (VDstIn.isMachineOpcode() in PostISelFolding()
10417 && VDstIn.getMachineOpcode() == AMDGPU::IMPLICIT_DEF) in PostISelFolding()
|
| /dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIISelLowering.cpp | 10415 SDValue VDstIn = Node->getOperand(6); in PostISelFolding() local
10416 if (VDstIn.isMachineOpcode() in PostISelFolding()
10417 && VDstIn.getMachineOpcode() == AMDGPU::IMPLICIT_DEF) in PostISelFolding()
|