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Searched refs:VENDOR_CAP_PCI_DEV_OFFSET (Results 1 – 14 of 14) sorted by relevance

/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/roms/skiboot/hw/
H A Dnpu2.c49 #define VENDOR_CAP_PCI_DEV_OFFSET 0x0d macro
153 VENDOR_CAP_PCI_DEV_OFFSET, 1, ndev->link_flags); in npu2_set_link_flag()
160 VENDOR_CAP_PCI_DEV_OFFSET, 1, ndev->link_flags); in npu2_clear_link_flag()
H A Dnpu.c124 #define VENDOR_CAP_PCI_DEV_OFFSET 0x0d macro
391 VENDOR_CAP_PCI_DEV_OFFSET, 1, 0x01); in npu_dev_bind_pci_dev()
/dports/emulators/qemu42/qemu-4.2.1/roms/skiboot/hw/
H A Dnpu.c124 #define VENDOR_CAP_PCI_DEV_OFFSET 0x0d macro
391 VENDOR_CAP_PCI_DEV_OFFSET, 1, 0x01); in npu_dev_bind_pci_dev()
H A Dnpu2.c44 #define VENDOR_CAP_PCI_DEV_OFFSET 0x0d macro
67 VENDOR_CAP_PCI_DEV_OFFSET, 1, ndev->nvlink.link_flags); in npu2_set_link_flag()
74 VENDOR_CAP_PCI_DEV_OFFSET, 1, ndev->nvlink.link_flags); in npu2_clear_link_flag()
/dports/emulators/qemu5/qemu-5.2.0/roms/skiboot/hw/
H A Dnpu.c124 #define VENDOR_CAP_PCI_DEV_OFFSET 0x0d macro
391 VENDOR_CAP_PCI_DEV_OFFSET, 1, 0x01); in npu_dev_bind_pci_dev()
H A Dnpu2.c44 #define VENDOR_CAP_PCI_DEV_OFFSET 0x0d macro
67 VENDOR_CAP_PCI_DEV_OFFSET, 1, ndev->nvlink.link_flags); in npu2_set_link_flag()
74 VENDOR_CAP_PCI_DEV_OFFSET, 1, ndev->nvlink.link_flags); in npu2_clear_link_flag()
/dports/emulators/qemu-utils/qemu-4.2.1/roms/skiboot/hw/
H A Dnpu.c124 #define VENDOR_CAP_PCI_DEV_OFFSET 0x0d macro
391 VENDOR_CAP_PCI_DEV_OFFSET, 1, 0x01); in npu_dev_bind_pci_dev()
H A Dnpu2.c44 #define VENDOR_CAP_PCI_DEV_OFFSET 0x0d macro
67 VENDOR_CAP_PCI_DEV_OFFSET, 1, ndev->nvlink.link_flags); in npu2_set_link_flag()
74 VENDOR_CAP_PCI_DEV_OFFSET, 1, ndev->nvlink.link_flags); in npu2_clear_link_flag()
/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/skiboot/hw/
H A Dnpu.c124 #define VENDOR_CAP_PCI_DEV_OFFSET 0x0d
391 VENDOR_CAP_PCI_DEV_OFFSET, 1, 0x01);
H A Dnpu2.c44 #define VENDOR_CAP_PCI_DEV_OFFSET 0x0d macro
67 VENDOR_CAP_PCI_DEV_OFFSET, 1, ndev->nvlink.link_flags); in npu2_set_link_flag()
74 VENDOR_CAP_PCI_DEV_OFFSET, 1, ndev->nvlink.link_flags); in npu2_clear_link_flag()
/dports/emulators/qemu/qemu-6.2.0/roms/skiboot/hw/
H A Dnpu.c116 #define VENDOR_CAP_PCI_DEV_OFFSET 0x0d macro
383 VENDOR_CAP_PCI_DEV_OFFSET, 1, 0x01); in npu_dev_bind_pci_dev()
H A Dnpu2.c37 #define VENDOR_CAP_PCI_DEV_OFFSET 0x0d macro
60 VENDOR_CAP_PCI_DEV_OFFSET, 1, ndev->nvlink.link_flags); in npu2_set_link_flag()
67 VENDOR_CAP_PCI_DEV_OFFSET, 1, ndev->nvlink.link_flags); in npu2_clear_link_flag()
/dports/emulators/qemu60/qemu-6.0.0/roms/skiboot/hw/
H A Dnpu.c124 #define VENDOR_CAP_PCI_DEV_OFFSET 0x0d macro
391 VENDOR_CAP_PCI_DEV_OFFSET, 1, 0x01); in npu_dev_bind_pci_dev()
H A Dnpu2.c44 #define VENDOR_CAP_PCI_DEV_OFFSET 0x0d macro
67 VENDOR_CAP_PCI_DEV_OFFSET, 1, ndev->nvlink.link_flags); in npu2_set_link_flag()
74 VENDOR_CAP_PCI_DEV_OFFSET, 1, ndev->nvlink.link_flags); in npu2_clear_link_flag()