/dports/devel/llvm80/llvm-8.0.1.src/lib/Target/AMDGPU/ |
H A D | SIMachineFunctionInfo.cpp | 269 unsigned VGPRIndex = (NumVGPRSpillLanes % WaveSize); in addDefsUsesToList() 271 if (VGPRIndex == 0) { in addDefsUsesToList() 297 SpillLanes.push_back(SpilledReg(LaneVGPR, VGPRIndex)); in addDefsUsesToList()
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/dports/devel/llvm70/llvm-7.0.1.src/lib/Target/AMDGPU/ |
H A D | SIMachineFunctionInfo.cpp | 274 unsigned VGPRIndex = (NumVGPRSpillLanes % WaveSize); in allocateSGPRSpillToVGPR() local 276 if (VGPRIndex == 0) { in allocateSGPRSpillToVGPR() 302 SpillLanes.push_back(SpilledReg(LaneVGPR, VGPRIndex)); in allocateSGPRSpillToVGPR()
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/dports/devel/llvm10/llvm-10.0.1.src/lib/Target/AMDGPU/ |
H A D | SIMachineFunctionInfo.cpp | 286 unsigned VGPRIndex = (NumVGPRSpillLanes % WaveSize); in allocateSGPRSpillToVGPR() local 288 if (VGPRIndex == 0) { in allocateSGPRSpillToVGPR() 314 SpillLanes.push_back(SpilledReg(LaneVGPR, VGPRIndex)); in allocateSGPRSpillToVGPR()
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/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
H A D | SIMachineFunctionInfo.cpp | 286 unsigned VGPRIndex = (NumVGPRSpillLanes % WaveSize); in allocateSGPRSpillToVGPR() local 288 if (VGPRIndex == 0) { in allocateSGPRSpillToVGPR() 314 SpillLanes.push_back(SpilledReg(LaneVGPR, VGPRIndex)); in allocateSGPRSpillToVGPR()
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/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | SIMachineFunctionInfo.cpp | 286 unsigned VGPRIndex = (NumVGPRSpillLanes % WaveSize); in allocateSGPRSpillToVGPR() local 288 if (VGPRIndex == 0) { in allocateSGPRSpillToVGPR() 314 SpillLanes.push_back(SpilledReg(LaneVGPR, VGPRIndex)); in allocateSGPRSpillToVGPR()
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/dports/devel/llvm90/llvm-9.0.1.src/lib/Target/AMDGPU/ |
H A D | SIMachineFunctionInfo.cpp | 288 unsigned VGPRIndex = (NumVGPRSpillLanes % WaveSize); in allocateSGPRSpillToVGPR() local 290 if (VGPRIndex == 0) { in allocateSGPRSpillToVGPR() 316 SpillLanes.push_back(SpilledReg(LaneVGPR, VGPRIndex)); in allocateSGPRSpillToVGPR()
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/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/lib/Target/AMDGPU/ |
H A D | SIMachineFunctionInfo.cpp | 308 unsigned VGPRIndex = (NumVGPRSpillLanes % WaveSize); in allocateSGPRSpillToVGPR() local 319 } else if (VGPRIndex == 0) { in allocateSGPRSpillToVGPR() 345 SpillLanes.push_back(SpilledReg(LaneVGPR, VGPRIndex)); in allocateSGPRSpillToVGPR()
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/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/lib/Target/AMDGPU/ |
H A D | SIMachineFunctionInfo.cpp | 304 unsigned VGPRIndex = (NumVGPRSpillLanes % WaveSize); in allocateSGPRSpillToVGPR() local 315 } else if (VGPRIndex == 0) { in allocateSGPRSpillToVGPR() 341 SpillLanes.push_back(SpilledReg(LaneVGPR, VGPRIndex)); in allocateSGPRSpillToVGPR()
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/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/lib/Target/AMDGPU/ |
H A D | SIMachineFunctionInfo.cpp | 294 unsigned VGPRIndex = (NumVGPRSpillLanes % WaveSize); in allocateSGPRSpillToVGPR() local 305 } else if (VGPRIndex == 0) { in allocateSGPRSpillToVGPR() 331 SpillLanes.push_back(SpilledReg(LaneVGPR, VGPRIndex)); in allocateSGPRSpillToVGPR()
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/dports/devel/llvm11/llvm-11.0.1.src/lib/Target/AMDGPU/ |
H A D | SIMachineFunctionInfo.cpp | 304 unsigned VGPRIndex = (NumVGPRSpillLanes % WaveSize); in allocateSGPRSpillToVGPR() local 315 } else if (VGPRIndex == 0) { in allocateSGPRSpillToVGPR() 341 SpillLanes.push_back(SpilledReg(LaneVGPR, VGPRIndex)); in allocateSGPRSpillToVGPR()
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/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/lib/Target/AMDGPU/ |
H A D | SIMachineFunctionInfo.cpp | 294 unsigned VGPRIndex = (NumVGPRSpillLanes % WaveSize); in allocateSGPRSpillToVGPR() local 305 } else if (VGPRIndex == 0) { in allocateSGPRSpillToVGPR() 331 SpillLanes.push_back(SpilledReg(LaneVGPR, VGPRIndex)); in allocateSGPRSpillToVGPR()
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/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/lib/Target/AMDGPU/ |
H A D | SIMachineFunctionInfo.cpp | 315 unsigned VGPRIndex = (NumVGPRSpillLanes % WaveSize); in runOnMachineFunction() 326 } else if (VGPRIndex == 0) { in runOnMachineFunction() 360 SpillLanes.push_back(SpilledReg(LaneVGPR, VGPRIndex)); in runOnMachineFunction()
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/dports/graphics/llvm-mesa/llvm-13.0.1.src/lib/Target/AMDGPU/ |
H A D | SIMachineFunctionInfo.cpp | 315 unsigned VGPRIndex = (NumVGPRSpillLanes % WaveSize); in allocateSGPRSpillToVGPR() local 326 } else if (VGPRIndex == 0) { in allocateSGPRSpillToVGPR() 360 SpillLanes.push_back(SpilledReg(LaneVGPR, VGPRIndex)); in allocateSGPRSpillToVGPR()
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/dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/lib/Target/AMDGPU/ |
H A D | SIMachineFunctionInfo.cpp | 315 unsigned VGPRIndex = (NumVGPRSpillLanes % WaveSize); in allocateSGPRSpillToVGPR() local 326 } else if (VGPRIndex == 0) { in allocateSGPRSpillToVGPR() 360 SpillLanes.push_back(SpilledReg(LaneVGPR, VGPRIndex)); in allocateSGPRSpillToVGPR()
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/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/lib/Target/AMDGPU/ |
H A D | SIMachineFunctionInfo.cpp | 310 unsigned VGPRIndex = (NumVGPRSpillLanes % WaveSize); in allocateSGPRSpillToVGPR() local 321 } else if (VGPRIndex == 0) { in allocateSGPRSpillToVGPR() 355 SpillLanes.push_back(SpilledReg(LaneVGPR, VGPRIndex)); in allocateSGPRSpillToVGPR()
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/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/lib/Target/AMDGPU/ |
H A D | SIMachineFunctionInfo.cpp | 315 unsigned VGPRIndex = (NumVGPRSpillLanes % WaveSize); in allocateSGPRSpillToVGPR() local 326 } else if (VGPRIndex == 0) { in allocateSGPRSpillToVGPR() 360 SpillLanes.push_back(SpilledReg(LaneVGPR, VGPRIndex)); in allocateSGPRSpillToVGPR()
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/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/lib/Target/AMDGPU/ |
H A D | SIMachineFunctionInfo.cpp | 315 unsigned VGPRIndex = (NumVGPRSpillLanes % WaveSize); in allocateSGPRSpillToVGPR() local 326 } else if (VGPRIndex == 0) { in allocateSGPRSpillToVGPR() 360 SpillLanes.push_back(SpilledReg(LaneVGPR, VGPRIndex)); in allocateSGPRSpillToVGPR()
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