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Searched refs:VI_VV_LOOP_REDUCTION (Results 1 – 7 of 7) sorted by relevance

/dports/emulators/riscv-isa-sim/riscv-isa-sim-4f12984/riscv/insns/
H A Dvredsum_vs.h2 VI_VV_LOOP_REDUCTION
H A Dvredor_vs.h2 VI_VV_LOOP_REDUCTION
H A Dvredand_vs.h2 VI_VV_LOOP_REDUCTION
H A Dvredxor_vs.h2 VI_VV_LOOP_REDUCTION
H A Dvredmin_vs.h2 VI_VV_LOOP_REDUCTION
H A Dvredmax_vs.h2 VI_VV_LOOP_REDUCTION
/dports/emulators/riscv-isa-sim/riscv-isa-sim-4f12984/riscv/
H A Ddecode.h963 #define VI_VV_LOOP_REDUCTION(BODY) \ macro