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Searched refs:VI_WIDE_WVX_OP (Results 1 – 9 of 9) sorted by relevance

/dports/emulators/riscv-isa-sim/riscv-isa-sim-4f12984/riscv/insns/
H A Dvwadd_wv.h5 VI_WIDE_WVX_OP(vs1, +, int);
H A Dvwadd_wx.h5 VI_WIDE_WVX_OP(rs1, +, int);
H A Dvwsub_wv.h5 VI_WIDE_WVX_OP(vs1, -, int);
H A Dvwsub_wx.h5 VI_WIDE_WVX_OP(rs1, -, int);
H A Dvwsubu_wx.h5 VI_WIDE_WVX_OP(rs1, -, uint);
H A Dvwaddu_wv.h5 VI_WIDE_WVX_OP(vs1, +, uint);
H A Dvwaddu_wx.h5 VI_WIDE_WVX_OP(rs1, +, uint);
H A Dvwsubu_wv.h5 VI_WIDE_WVX_OP(vs1, -, uint);
/dports/emulators/riscv-isa-sim/riscv-isa-sim-4f12984/riscv/
H A Ddecode.h1274 #define VI_WIDE_WVX_OP(var0, op0, sign) \ macro