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Searched refs:VirtualReg (Results 1 – 25 of 142) sorted by relevance

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/dports/mail/thunderbird/thunderbird-91.8.0/third_party/rust/regalloc/src/
H A Dreg_maps.rs1 use crate::{RealReg, RegUsageMapper, VirtualReg};
23 overlay: SmallVec<[(VirtualReg, RealReg); 16]>,
148 fn get_use(&self, vreg: VirtualReg) -> Option<RealReg> { in get_use()
156 fn get_def(&self, vreg: VirtualReg) -> Option<RealReg> { in get_def()
165 fn get_mod(&self, vreg: VirtualReg) -> Option<RealReg> { in get_mod()
175 use crate::{Reg, RegClass, VirtualReg};
177 fn vreg(idx: u32) -> VirtualReg { in vreg() argument
304 uses: SmallVec<[(VirtualReg, RealReg); 8]>,
307 defs: SmallVec<[(VirtualReg, RealReg); 8]>,
336 fn get_use(&self, vreg: VirtualReg) -> Option<RealReg> { in get_use()
[all …]
H A Dlib.rs60 pub use crate::data_structures::VirtualReg;
166 fn get_use(&self, vreg: VirtualReg) -> Option<RealReg>; in get_use()
170 fn get_def(&self, vreg: VirtualReg) -> Option<RealReg>; in get_def()
174 fn get_mod(&self, vreg: VirtualReg) -> Option<RealReg>; in get_mod()
289 fn get_spillslot_size(&self, regclass: RegClass, for_vreg: VirtualReg) -> u32; in get_spillslot_size()
301 for_vreg: Option<VirtualReg>, in gen_spill() argument
312 for_vreg: Option<VirtualReg>, in gen_reload() argument
322 for_vreg: VirtualReg, in gen_move() argument
342 reg: VirtualReg, in maybe_direct_reload() argument
492 pub reftyped_vregs: Vec<VirtualReg>,
H A Dsnapshot.rs20 Spill { vreg: Option<VirtualReg> },
21 Reload { vreg: Option<VirtualReg> },
22 Move { vreg: VirtualReg },
261 for_vreg: Option<VirtualReg>, in gen_spill() argument
274 for_vreg: Option<VirtualReg>, in gen_reload() argument
287 for_vreg: VirtualReg, in gen_move() argument
305 fn get_spillslot_size(&self, regclass: RegClass, for_vreg: VirtualReg) -> u32 { in get_spillslot_size()
315 _reg: VirtualReg, in maybe_direct_reload() argument
H A Dinst_stream.rs5 TypedIxVec, VirtualReg, Writable,
20 for_vreg: Option<VirtualReg>,
25 for_vreg: Option<VirtualReg>,
30 for_vreg: VirtualReg,
219 frag_map: Vec<(RangeFrag, VirtualReg, RealReg)>, in map_vregs_to_rregs() argument
226 reftyped_vregs: &[VirtualReg], in map_vregs_to_rregs() argument
636 frag_map: Vec<(RangeFrag, VirtualReg, RealReg)>, in edit_inst_stream() argument
640 reftyped_vregs: &[VirtualReg], in edit_inst_stream() argument
/dports/sysutils/vector/vector-0.10.0/cargo-crates/regalloc-0.0.25/src/
H A Dreg_maps.rs1 use crate::{RealReg, RegUsageMapper, VirtualReg};
23 overlay: SmallVec<[(VirtualReg, RealReg); 16]>,
148 fn get_use(&self, vreg: VirtualReg) -> Option<RealReg> { in get_use()
156 fn get_def(&self, vreg: VirtualReg) -> Option<RealReg> { in get_def()
165 fn get_mod(&self, vreg: VirtualReg) -> Option<RealReg> { in get_mod()
175 use crate::{Reg, RegClass, VirtualReg};
177 fn vreg(idx: u32) -> VirtualReg { in vreg() argument
304 uses: SmallVec<[(VirtualReg, RealReg); 8]>,
307 defs: SmallVec<[(VirtualReg, RealReg); 8]>,
336 fn get_use(&self, vreg: VirtualReg) -> Option<RealReg> { in get_use()
[all …]
H A Dlib.rs54 pub use crate::data_structures::VirtualReg;
160 fn get_use(&self, vreg: VirtualReg) -> Option<RealReg>; in get_use()
164 fn get_def(&self, vreg: VirtualReg) -> Option<RealReg>; in get_def()
168 fn get_mod(&self, vreg: VirtualReg) -> Option<RealReg>; in get_mod()
265 fn get_spillslot_size(&self, regclass: RegClass, for_vreg: VirtualReg) -> u32; in get_spillslot_size()
273 fn gen_spill(&self, to_slot: SpillSlot, from_reg: RealReg, for_vreg: VirtualReg) -> Self::Inst; in gen_spill()
283 for_vreg: VirtualReg, in gen_reload() argument
293 for_vreg: VirtualReg, in gen_move() argument
313 reg: VirtualReg, in maybe_direct_reload() argument
/dports/www/firefox/firefox-99.0/third_party/rust/regalloc/src/
H A Dreg_maps.rs1 use crate::{RealReg, RegUsageMapper, VirtualReg};
23 overlay: SmallVec<[(VirtualReg, RealReg); 16]>,
148 fn get_use(&self, vreg: VirtualReg) -> Option<RealReg> { in get_use()
156 fn get_def(&self, vreg: VirtualReg) -> Option<RealReg> { in get_def()
165 fn get_mod(&self, vreg: VirtualReg) -> Option<RealReg> { in get_mod()
175 use crate::{Reg, RegClass, VirtualReg};
177 fn vreg(idx: u32) -> VirtualReg { in vreg() argument
304 uses: SmallVec<[(VirtualReg, RealReg); 8]>,
307 defs: SmallVec<[(VirtualReg, RealReg); 8]>,
336 fn get_use(&self, vreg: VirtualReg) -> Option<RealReg> { in get_use()
[all …]
H A Dlib.rs60 pub use crate::data_structures::VirtualReg;
166 fn get_use(&self, vreg: VirtualReg) -> Option<RealReg>; in get_use()
170 fn get_def(&self, vreg: VirtualReg) -> Option<RealReg>; in get_def()
174 fn get_mod(&self, vreg: VirtualReg) -> Option<RealReg>; in get_mod()
289 fn get_spillslot_size(&self, regclass: RegClass, for_vreg: VirtualReg) -> u32; in get_spillslot_size()
301 for_vreg: Option<VirtualReg>, in gen_spill() argument
312 for_vreg: Option<VirtualReg>, in gen_reload() argument
322 for_vreg: VirtualReg, in gen_move() argument
342 reg: VirtualReg, in maybe_direct_reload() argument
492 pub reftyped_vregs: Vec<VirtualReg>,
H A Dsnapshot.rs20 Spill { vreg: Option<VirtualReg> },
21 Reload { vreg: Option<VirtualReg> },
22 Move { vreg: VirtualReg },
261 for_vreg: Option<VirtualReg>, in gen_spill() argument
274 for_vreg: Option<VirtualReg>, in gen_reload() argument
287 for_vreg: VirtualReg, in gen_move() argument
305 fn get_spillslot_size(&self, regclass: RegClass, for_vreg: VirtualReg) -> u32 { in get_spillslot_size()
315 _reg: VirtualReg, in maybe_direct_reload() argument
H A Dinst_stream.rs5 TypedIxVec, VirtualReg, Writable,
20 for_vreg: Option<VirtualReg>,
25 for_vreg: Option<VirtualReg>,
30 for_vreg: VirtualReg,
219 frag_map: Vec<(RangeFrag, VirtualReg, RealReg)>, in map_vregs_to_rregs() argument
226 reftyped_vregs: &[VirtualReg], in map_vregs_to_rregs() argument
636 frag_map: Vec<(RangeFrag, VirtualReg, RealReg)>, in edit_inst_stream() argument
640 reftyped_vregs: &[VirtualReg], in edit_inst_stream() argument
/dports/lang/rust/rustc-1.58.1-src/vendor/regalloc/src/
H A Dreg_maps.rs1 use crate::{RealReg, RegUsageMapper, VirtualReg};
23 overlay: SmallVec<[(VirtualReg, RealReg); 16]>,
148 fn get_use(&self, vreg: VirtualReg) -> Option<RealReg> { in get_use()
156 fn get_def(&self, vreg: VirtualReg) -> Option<RealReg> { in get_def()
165 fn get_mod(&self, vreg: VirtualReg) -> Option<RealReg> { in get_mod()
175 use crate::{Reg, RegClass, VirtualReg};
177 fn vreg(idx: u32) -> VirtualReg { in vreg() argument
304 uses: SmallVec<[(VirtualReg, RealReg); 8]>,
307 defs: SmallVec<[(VirtualReg, RealReg); 8]>,
336 fn get_use(&self, vreg: VirtualReg) -> Option<RealReg> { in get_use()
[all …]
H A Dlib.rs60 pub use crate::data_structures::VirtualReg;
166 fn get_use(&self, vreg: VirtualReg) -> Option<RealReg>; in get_use()
170 fn get_def(&self, vreg: VirtualReg) -> Option<RealReg>; in get_def()
174 fn get_mod(&self, vreg: VirtualReg) -> Option<RealReg>; in get_mod()
289 fn get_spillslot_size(&self, regclass: RegClass, for_vreg: VirtualReg) -> u32; in get_spillslot_size()
301 for_vreg: Option<VirtualReg>, in gen_spill() argument
312 for_vreg: Option<VirtualReg>, in gen_reload() argument
322 for_vreg: VirtualReg, in gen_move() argument
342 reg: VirtualReg, in maybe_direct_reload() argument
492 pub reftyped_vregs: Vec<VirtualReg>,
H A Dsnapshot.rs20 Spill { vreg: Option<VirtualReg> },
21 Reload { vreg: Option<VirtualReg> },
22 Move { vreg: VirtualReg },
261 for_vreg: Option<VirtualReg>, in gen_spill() argument
274 for_vreg: Option<VirtualReg>, in gen_reload() argument
287 for_vreg: VirtualReg, in gen_move() argument
305 fn get_spillslot_size(&self, regclass: RegClass, for_vreg: VirtualReg) -> u32 { in get_spillslot_size()
315 _reg: VirtualReg, in maybe_direct_reload() argument
H A Dinst_stream.rs5 TypedIxVec, VirtualReg, Writable,
20 for_vreg: Option<VirtualReg>,
25 for_vreg: Option<VirtualReg>,
30 for_vreg: VirtualReg,
219 frag_map: Vec<(RangeFrag, VirtualReg, RealReg)>, in map_vregs_to_rregs() argument
226 reftyped_vregs: &[VirtualReg], in map_vregs_to_rregs() argument
636 frag_map: Vec<(RangeFrag, VirtualReg, RealReg)>, in edit_inst_stream() argument
640 reftyped_vregs: &[VirtualReg], in edit_inst_stream() argument
/dports/www/firefox-esr/firefox-91.8.0/third_party/rust/regalloc/src/
H A Dreg_maps.rs1 use crate::{RealReg, RegUsageMapper, VirtualReg};
23 overlay: SmallVec<[(VirtualReg, RealReg); 16]>,
148 fn get_use(&self, vreg: VirtualReg) -> Option<RealReg> { in get_use()
156 fn get_def(&self, vreg: VirtualReg) -> Option<RealReg> { in get_def()
165 fn get_mod(&self, vreg: VirtualReg) -> Option<RealReg> { in get_mod()
175 use crate::{Reg, RegClass, VirtualReg};
177 fn vreg(idx: u32) -> VirtualReg { in vreg() argument
304 uses: SmallVec<[(VirtualReg, RealReg); 8]>,
307 defs: SmallVec<[(VirtualReg, RealReg); 8]>,
336 fn get_use(&self, vreg: VirtualReg) -> Option<RealReg> { in get_use()
[all …]
H A Dlib.rs60 pub use crate::data_structures::VirtualReg;
166 fn get_use(&self, vreg: VirtualReg) -> Option<RealReg>; in get_use()
170 fn get_def(&self, vreg: VirtualReg) -> Option<RealReg>; in get_def()
174 fn get_mod(&self, vreg: VirtualReg) -> Option<RealReg>; in get_mod()
289 fn get_spillslot_size(&self, regclass: RegClass, for_vreg: VirtualReg) -> u32; in get_spillslot_size()
301 for_vreg: Option<VirtualReg>, in gen_spill() argument
312 for_vreg: Option<VirtualReg>, in gen_reload() argument
322 for_vreg: VirtualReg, in gen_move() argument
342 reg: VirtualReg, in maybe_direct_reload() argument
492 pub reftyped_vregs: Vec<VirtualReg>,
H A Dsnapshot.rs20 Spill { vreg: Option<VirtualReg> },
21 Reload { vreg: Option<VirtualReg> },
22 Move { vreg: VirtualReg },
261 for_vreg: Option<VirtualReg>, in gen_spill() argument
274 for_vreg: Option<VirtualReg>, in gen_reload() argument
287 for_vreg: VirtualReg, in gen_move() argument
305 fn get_spillslot_size(&self, regclass: RegClass, for_vreg: VirtualReg) -> u32 { in get_spillslot_size()
315 _reg: VirtualReg, in maybe_direct_reload() argument
/dports/devel/hs-hlint/hlint-3.3.4/_cabal_deps/ghc-lib-parser-9.0.1.20210324/compiler/GHC/Platform/
H A DReg.hs15 VirtualReg(..),
55 data VirtualReg type
68 instance Ord VirtualReg where
83 instance Uniquable VirtualReg where
91 instance Outputable VirtualReg where
104 renameVirtualReg :: Unique -> VirtualReg -> VirtualReg
113 classOfVirtualReg :: VirtualReg -> RegClass
126 getHiVirtualRegFromLo :: VirtualReg -> VirtualReg
180 = RegVirtual !VirtualReg
231 takeVirtualReg :: Reg -> Maybe VirtualReg
[all …]
/dports/devel/hs-ormolu/ormolu-0.4.0.0/_cabal_deps/ghc-lib-parser-9.2.1.20211101/compiler/GHC/Platform/
H A DReg.hs15 VirtualReg(..),
57 data VirtualReg type
70 instance Ord VirtualReg where
85 instance Uniquable VirtualReg where
93 instance Outputable VirtualReg where
106 renameVirtualReg :: Unique -> VirtualReg -> VirtualReg
115 classOfVirtualReg :: VirtualReg -> RegClass
128 getHiVirtualRegFromLo :: VirtualReg -> VirtualReg
182 = RegVirtual !VirtualReg
233 takeVirtualReg :: Reg -> Maybe VirtualReg
[all …]
/dports/lang/ghc/ghc-8.10.7/compiler/nativeGen/
H A DReg.hs14 VirtualReg(..),
54 data VirtualReg type
67 instance Ord VirtualReg where
82 instance Uniquable VirtualReg where
90 instance Outputable VirtualReg where
103 renameVirtualReg :: Unique -> VirtualReg -> VirtualReg
112 classOfVirtualReg :: VirtualReg -> RegClass
125 getHiVirtualRegFromLo :: VirtualReg -> VirtualReg
179 = RegVirtual !VirtualReg
227 takeVirtualReg :: Reg -> Maybe VirtualReg
[all …]
/dports/lang/ghc/ghc-8.10.7/compiler/nativeGen/RegAlloc/Graph/
H A DSpillCost.hs43 = ( VirtualReg -- register name
159 takeVirtuals :: UniqSet Reg -> UniqSet VirtualReg
168 -> Graph VirtualReg RegClass RealReg
169 -> VirtualReg
254 -> Graph VirtualReg RegClass RealReg
255 -> VirtualReg
278 :: (VirtualReg -> RegClass)
279 -> Graph VirtualReg RegClass RealReg
280 -> VirtualReg
302 :: (VirtualReg -> RegClass)
[all …]
H A DMain.hs98 -> Color.Triv VirtualReg RegClass RealReg
110 , Color.Graph VirtualReg RegClass RealReg)
138 (graph :: Color.Graph VirtualReg RegClass RealReg)
330 -> Color.Graph VirtualReg RegClass RealReg
331 -> Color.Graph VirtualReg RegClass RealReg
353 -> Color.Graph VirtualReg RegClass RealReg
354 -> Color.Graph VirtualReg RegClass RealReg
423 seqGraph :: Color.Graph VirtualReg RegClass RealReg -> ()
433 seqNode :: Color.Node VirtualReg RegClass RealReg -> ()
444 seqVirtualReg :: VirtualReg -> ()
[all …]
H A DStats.hs43 , raGraph :: Color.Graph VirtualReg RegClass RealReg
57 , raGraph :: Color.Graph VirtualReg RegClass RealReg
60 , raCoalesced :: UniqFM VirtualReg
78 , raGraph :: Color.Graph VirtualReg RegClass RealReg
81 , raGraphColored :: Color.Graph VirtualReg RegClass RealReg
84 , raCoalesced :: UniqFM VirtualReg
188 -> Color.Graph VirtualReg RegClass RealReg
235 binLifetimeCount :: UniqFM (VirtualReg, Int) -> UniqFM (Int, Int)
268 -> Color.Graph VirtualReg RegClass RealReg -- ^ global register conflict graph
/dports/lang/spidermonkey78/firefox-78.9.0/third_party/rust/regalloc/src/
H A Dlib.rs52 pub use crate::data_structures::VirtualReg;
248 fn get_spillslot_size(&self, regclass: RegClass, for_vreg: VirtualReg) -> u32; in get_spillslot_size()
256 fn gen_spill(&self, to_slot: SpillSlot, from_reg: RealReg, for_vreg: VirtualReg) -> Self::Inst; in gen_spill()
266 for_vreg: VirtualReg, in gen_reload() argument
276 for_vreg: VirtualReg, in gen_move() argument
296 reg: VirtualReg, in maybe_direct_reload() argument
H A Ddata_structures.rs710 Some(VirtualReg { reg: self }) in as_virtual_reg()
806 pub struct VirtualReg { struct
810 pub fn to_virtual_reg(self) -> VirtualReg { in to_virtual_reg() argument
812 VirtualReg { reg: self } in to_virtual_reg()
818 impl VirtualReg { impl
828 pub fn invalid() -> VirtualReg { in invalid()
829 VirtualReg { in invalid()
840 if self == VirtualReg::invalid() { in maybe_valid()
847 impl fmt::Debug for VirtualReg { implementation
2118 pub vreg: VirtualReg,
[all …]

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