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Searched refs:WREAL (Results 1 – 5 of 5) sorted by relevance

/dports/cad/verilator/verilator-4.216/src/
H A DV3ParseGrammar.cpp160 if (GRAMMARP->m_varDecl == AstVarType::WREAL) { in createVariable()
H A DV3Ast.h699 WREAL, enumerator
729 return (m_e == WIRE || m_e == WREAL || m_e == IMPLICITWIRE || m_e == TRIWIRE || m_e == TRI0 in isSignal()
733 return (m_e == SUPPLY0 || m_e == SUPPLY1 || m_e == WIRE || m_e == WREAL in isContAssignable()
H A DV3SplitVar.cpp147 = type == type.VAR || type == type.WIRE || type == type.PORT || type == type.WREAL; in cannotSplitVarTypeReason()
H A DV3AstNodes.cpp308 } else if (varType() == AstVarType::WREAL) { in verilogKwd()
H A Dverilog.y1712 | yWREAL { VARDECL(WREAL); }