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/dports/cad/ghdl/ghdl-1.0.0/src/synth/
H A Dsynth-environment-debug.adb34 W_Rec : Wire_Id_Record renames Wire_Id_Table.Table (Wid); variable
38 Put_Line (" kind: " & Wire_Kind'Image (W_Rec.Kind));
39 Put_Line (" decl:" & Source.Syn_Src'Image (W_Rec.Decl));
41 Dump_Net_Name (W_Rec.Gate, True);
43 Put_Line (" cur_assign:" & Seq_Assign'Image (W_Rec.Cur_Assign));
44 Put_Line (" conc_assign:" & Conc_Assign'Image(W_Rec.Final_Assign));
87 W_Rec : Wire_Id_Record renames Wire_Id_Table.Table (Rec.Id); variable
89 Put_Line (" wire decl:" & Source.Syn_Src'Image (W_Rec.Decl));
91 Dump_Net_Name (W_Rec.Gate, True);