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Searched refs:XHC_1_MILLISECOND (Results 1 – 25 of 71) sorted by relevance

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/dports/sysutils/uefi-edk2-bhyve-csm/uefi-edk2-aa8d718/MdeModulePkg/Bus/Pci/XhciPei/
H A DXhcPeim.h46 #define XHC_1_MILLISECOND (1000 * XHC_1_MICROSECOND) macro
47 #define XHC_1_SECOND (1000 * XHC_1_MILLISECOND)
58 #define XHC_POLL_DELAY (1 * XHC_1_MILLISECOND)
63 #define XHC_ROOT_PORT_STATE_STABLE (200 * XHC_1_MILLISECOND)
65 #define XHC_GENERIC_TIMEOUT (10 * XHC_1_MILLISECOND)
/dports/emulators/qemu42/qemu-4.2.1/roms/edk2/MdeModulePkg/Bus/Pci/XhciPei/
H A DXhcPeim.h41 #define XHC_1_MILLISECOND (1000 * XHC_1_MICROSECOND) macro
42 #define XHC_1_SECOND (1000 * XHC_1_MILLISECOND)
59 #define XHC_ROOT_PORT_STATE_STABLE (200 * XHC_1_MILLISECOND)
/dports/emulators/qemu-utils/qemu-4.2.1/roms/edk2/MdeModulePkg/Bus/Pci/XhciPei/
H A DXhcPeim.h41 #define XHC_1_MILLISECOND (1000 * XHC_1_MICROSECOND) macro
42 #define XHC_1_SECOND (1000 * XHC_1_MILLISECOND)
59 #define XHC_ROOT_PORT_STATE_STABLE (200 * XHC_1_MILLISECOND)
/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/edk2/MdeModulePkg/Bus/Pci/XhciPei/
H A DXhcPeim.h41 #define XHC_1_MILLISECOND (1000 * XHC_1_MICROSECOND) macro
42 #define XHC_1_SECOND (1000 * XHC_1_MILLISECOND)
59 #define XHC_ROOT_PORT_STATE_STABLE (200 * XHC_1_MILLISECOND)
/dports/emulators/qemu60/qemu-6.0.0/roms/edk2/MdeModulePkg/Bus/Pci/XhciPei/
H A DXhcPeim.h41 #define XHC_1_MILLISECOND (1000 * XHC_1_MICROSECOND) macro
42 #define XHC_1_SECOND (1000 * XHC_1_MILLISECOND)
59 #define XHC_ROOT_PORT_STATE_STABLE (200 * XHC_1_MILLISECOND)
/dports/emulators/qemu5/qemu-5.2.0/roms/edk2/MdeModulePkg/Bus/Pci/XhciPei/
H A DXhcPeim.h41 #define XHC_1_MILLISECOND (1000 * XHC_1_MICROSECOND) macro
42 #define XHC_1_SECOND (1000 * XHC_1_MILLISECOND)
59 #define XHC_ROOT_PORT_STATE_STABLE (200 * XHC_1_MILLISECOND)
/dports/sysutils/uefi-edk2-bhyve/edk2-edk2-stable202102/MdeModulePkg/Bus/Pci/XhciPei/
H A DXhcPeim.h41 #define XHC_1_MILLISECOND (1000 * XHC_1_MICROSECOND) macro
42 #define XHC_1_SECOND (1000 * XHC_1_MILLISECOND)
59 #define XHC_ROOT_PORT_STATE_STABLE (200 * XHC_1_MILLISECOND)
/dports/sysutils/uefi-edk2-qemu/edk2-edk2-stable201911/MdeModulePkg/Bus/Pci/XhciPei/
H A DXhcPeim.h41 #define XHC_1_MILLISECOND (1000 * XHC_1_MICROSECOND) macro
42 #define XHC_1_SECOND (1000 * XHC_1_MILLISECOND)
59 #define XHC_ROOT_PORT_STATE_STABLE (200 * XHC_1_MILLISECOND)
/dports/emulators/qemu/qemu-6.2.0/roms/edk2/MdeModulePkg/Bus/Pci/XhciPei/
H A DXhcPeim.h41 #define XHC_1_MILLISECOND (1000 * XHC_1_MICROSECOND) macro
42 #define XHC_1_SECOND (1000 * XHC_1_MILLISECOND)
59 #define XHC_ROOT_PORT_STATE_STABLE (200 * XHC_1_MILLISECOND)
/dports/sysutils/edk2/edk2-edk2-stable202102/MdeModulePkg/Bus/Pci/XhciPei/
H A DXhcPeim.h41 #define XHC_1_MILLISECOND (1000 * XHC_1_MICROSECOND) macro
42 #define XHC_1_SECOND (1000 * XHC_1_MILLISECOND)
59 #define XHC_ROOT_PORT_STATE_STABLE (200 * XHC_1_MILLISECOND)
/dports/emulators/qemu60/qemu-6.0.0/roms/edk2/MdeModulePkg/Bus/Pci/XhciDxe/
H A DXhciReg.c448 Loop = Timeout * XHC_1_MILLISECOND; in XhcWaitOpRegBit()
656 gBS->Stall (XHC_1_MILLISECOND); in XhcResetHC()
H A DXhci.h47 #define XHC_1_MILLISECOND (1000) macro
/dports/emulators/qemu42/qemu-4.2.1/roms/edk2/MdeModulePkg/Bus/Pci/XhciDxe/
H A DXhciReg.c448 Loop = Timeout * XHC_1_MILLISECOND; in XhcWaitOpRegBit()
656 gBS->Stall (XHC_1_MILLISECOND); in XhcResetHC()
H A DXhci.h46 #define XHC_1_MILLISECOND (1000) macro
/dports/emulators/qemu/qemu-6.2.0/roms/edk2/MdeModulePkg/Bus/Pci/XhciDxe/
H A DXhciReg.c448 Loop = Timeout * XHC_1_MILLISECOND; in XhcWaitOpRegBit()
656 gBS->Stall (XHC_1_MILLISECOND); in XhcResetHC()
H A DXhci.h47 #define XHC_1_MILLISECOND (1000) macro
/dports/emulators/qemu5/qemu-5.2.0/roms/edk2/MdeModulePkg/Bus/Pci/XhciDxe/
H A DXhciReg.c448 Loop = Timeout * XHC_1_MILLISECOND; in XhcWaitOpRegBit()
656 gBS->Stall (XHC_1_MILLISECOND); in XhcResetHC()
H A DXhci.h47 #define XHC_1_MILLISECOND (1000) macro
/dports/sysutils/uefi-edk2-qemu/edk2-edk2-stable201911/MdeModulePkg/Bus/Pci/XhciDxe/
H A DXhciReg.c448 Loop = Timeout * XHC_1_MILLISECOND; in XhcWaitOpRegBit()
656 gBS->Stall (XHC_1_MILLISECOND); in XhcResetHC()
/dports/emulators/qemu-utils/qemu-4.2.1/roms/edk2/MdeModulePkg/Bus/Pci/XhciDxe/
H A DXhciReg.c448 Loop = Timeout * XHC_1_MILLISECOND; in XhcWaitOpRegBit()
656 gBS->Stall (XHC_1_MILLISECOND); in XhcResetHC()
/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/edk2/MdeModulePkg/Bus/Pci/XhciDxe/
H A DXhciReg.c448 Loop = Timeout * XHC_1_MILLISECOND; in XhcWaitOpRegBit()
656 gBS->Stall (XHC_1_MILLISECOND); in XhcResetHC()
/dports/sysutils/edk2/edk2-platforms-89f6170d/Features/Intel/Debugging/Usb3DebugFeaturePkg/Library/Usb3DebugPortLib/
H A DMiscServices.c374 Loop = (Timeout * XHC_1_MILLISECOND / XHC_POLL_DELAY) + 1;
/dports/emulators/qemu60/qemu-6.0.0/roms/edk2/SourceLevelDebugPkg/Library/DebugCommunicationLibUsb3/
H A DDebugCommunicationLibUsb3Internal.h180 #define XHC_1_MILLISECOND (1000) macro
/dports/emulators/qemu/qemu-6.2.0/roms/edk2/SourceLevelDebugPkg/Library/DebugCommunicationLibUsb3/
H A DDebugCommunicationLibUsb3Internal.h180 #define XHC_1_MILLISECOND (1000) macro
/dports/emulators/qemu-utils/qemu-4.2.1/roms/edk2/SourceLevelDebugPkg/Library/DebugCommunicationLibUsb3/
H A DDebugCommunicationLibUsb3Internal.h180 #define XHC_1_MILLISECOND (1000) macro

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