| /dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/drivers/i2c/ |
| H A D | xilinx_xiic.c | 32 #define XIIC_CR_REG_OFFSET (0x00+XIIC_REG_OFFSET) /* Control Register */ macro
254 writeb(XIIC_CR_TX_FIFO_RESET_MASK, priv->base + XIIC_CR_REG_OFFSET); in xiic_reinit()
257 writeb(XIIC_CR_ENABLE_DEVICE_MASK, priv->base + XIIC_CR_REG_OFFSET); in xiic_reinit()
329 writel(XIIC_CR_TX_FIFO_RESET_MASK, priv->base + XIIC_CR_REG_OFFSET); in xilinx_xiic_probe()
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| /dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/drivers/i2c/ |
| H A D | xilinx_xiic.c | 32 #define XIIC_CR_REG_OFFSET (0x00+XIIC_REG_OFFSET) /* Control Register */ macro
254 writeb(XIIC_CR_TX_FIFO_RESET_MASK, priv->base + XIIC_CR_REG_OFFSET); in xiic_reinit()
257 writeb(XIIC_CR_ENABLE_DEVICE_MASK, priv->base + XIIC_CR_REG_OFFSET); in xiic_reinit()
329 writel(XIIC_CR_TX_FIFO_RESET_MASK, priv->base + XIIC_CR_REG_OFFSET); in xilinx_xiic_probe()
|
| /dports/sysutils/u-boot-olinuxino-lime2-emmc/u-boot-2021.07/drivers/i2c/ |
| H A D | xilinx_xiic.c | 32 #define XIIC_CR_REG_OFFSET (0x00+XIIC_REG_OFFSET) /* Control Register */ macro
254 writeb(XIIC_CR_TX_FIFO_RESET_MASK, priv->base + XIIC_CR_REG_OFFSET); in xiic_reinit()
257 writeb(XIIC_CR_ENABLE_DEVICE_MASK, priv->base + XIIC_CR_REG_OFFSET); in xiic_reinit()
329 writel(XIIC_CR_TX_FIFO_RESET_MASK, priv->base + XIIC_CR_REG_OFFSET); in xilinx_xiic_probe()
|
| /dports/sysutils/u-boot-chip/u-boot-2021.07/drivers/i2c/ |
| H A D | xilinx_xiic.c | 32 #define XIIC_CR_REG_OFFSET (0x00+XIIC_REG_OFFSET) /* Control Register */ macro
254 writeb(XIIC_CR_TX_FIFO_RESET_MASK, priv->base + XIIC_CR_REG_OFFSET); in xiic_reinit()
257 writeb(XIIC_CR_ENABLE_DEVICE_MASK, priv->base + XIIC_CR_REG_OFFSET); in xiic_reinit()
329 writel(XIIC_CR_TX_FIFO_RESET_MASK, priv->base + XIIC_CR_REG_OFFSET); in xilinx_xiic_probe()
|
| /dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/drivers/i2c/ |
| H A D | xilinx_xiic.c | 32 #define XIIC_CR_REG_OFFSET (0x00+XIIC_REG_OFFSET) /* Control Register */ macro
254 writeb(XIIC_CR_TX_FIFO_RESET_MASK, priv->base + XIIC_CR_REG_OFFSET); in xiic_reinit()
257 writeb(XIIC_CR_ENABLE_DEVICE_MASK, priv->base + XIIC_CR_REG_OFFSET); in xiic_reinit()
329 writel(XIIC_CR_TX_FIFO_RESET_MASK, priv->base + XIIC_CR_REG_OFFSET); in xilinx_xiic_probe()
|
| /dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/drivers/i2c/ |
| H A D | xilinx_xiic.c | 32 #define XIIC_CR_REG_OFFSET (0x00+XIIC_REG_OFFSET) /* Control Register */ macro
254 writeb(XIIC_CR_TX_FIFO_RESET_MASK, priv->base + XIIC_CR_REG_OFFSET); in xiic_reinit()
257 writeb(XIIC_CR_ENABLE_DEVICE_MASK, priv->base + XIIC_CR_REG_OFFSET); in xiic_reinit()
329 writel(XIIC_CR_TX_FIFO_RESET_MASK, priv->base + XIIC_CR_REG_OFFSET); in xilinx_xiic_probe()
|
| /dports/sysutils/u-boot-firefly-rk3399/u-boot-2021.07/drivers/i2c/ |
| H A D | xilinx_xiic.c | 32 #define XIIC_CR_REG_OFFSET (0x00+XIIC_REG_OFFSET) /* Control Register */ macro
254 writeb(XIIC_CR_TX_FIFO_RESET_MASK, priv->base + XIIC_CR_REG_OFFSET); in xiic_reinit()
257 writeb(XIIC_CR_ENABLE_DEVICE_MASK, priv->base + XIIC_CR_REG_OFFSET); in xiic_reinit()
329 writel(XIIC_CR_TX_FIFO_RESET_MASK, priv->base + XIIC_CR_REG_OFFSET); in xilinx_xiic_probe()
|
| /dports/sysutils/u-boot-sinovoip-bpi-m3/u-boot-2021.07/drivers/i2c/ |
| H A D | xilinx_xiic.c | 32 #define XIIC_CR_REG_OFFSET (0x00+XIIC_REG_OFFSET) /* Control Register */ macro
254 writeb(XIIC_CR_TX_FIFO_RESET_MASK, priv->base + XIIC_CR_REG_OFFSET); in xiic_reinit()
257 writeb(XIIC_CR_ENABLE_DEVICE_MASK, priv->base + XIIC_CR_REG_OFFSET); in xiic_reinit()
329 writel(XIIC_CR_TX_FIFO_RESET_MASK, priv->base + XIIC_CR_REG_OFFSET); in xilinx_xiic_probe()
|
| /dports/sysutils/u-boot-a13-olinuxino/u-boot-2021.07/drivers/i2c/ |
| H A D | xilinx_xiic.c | 32 #define XIIC_CR_REG_OFFSET (0x00+XIIC_REG_OFFSET) /* Control Register */ macro
254 writeb(XIIC_CR_TX_FIFO_RESET_MASK, priv->base + XIIC_CR_REG_OFFSET); in xiic_reinit()
257 writeb(XIIC_CR_ENABLE_DEVICE_MASK, priv->base + XIIC_CR_REG_OFFSET); in xiic_reinit()
329 writel(XIIC_CR_TX_FIFO_RESET_MASK, priv->base + XIIC_CR_REG_OFFSET); in xilinx_xiic_probe()
|
| /dports/sysutils/u-boot-sopine/u-boot-2021.07/drivers/i2c/ |
| H A D | xilinx_xiic.c | 32 #define XIIC_CR_REG_OFFSET (0x00+XIIC_REG_OFFSET) /* Control Register */ macro
254 writeb(XIIC_CR_TX_FIFO_RESET_MASK, priv->base + XIIC_CR_REG_OFFSET); in xiic_reinit()
257 writeb(XIIC_CR_ENABLE_DEVICE_MASK, priv->base + XIIC_CR_REG_OFFSET); in xiic_reinit()
329 writel(XIIC_CR_TX_FIFO_RESET_MASK, priv->base + XIIC_CR_REG_OFFSET); in xilinx_xiic_probe()
|
| /dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/drivers/i2c/ |
| H A D | xilinx_xiic.c | 32 #define XIIC_CR_REG_OFFSET (0x00+XIIC_REG_OFFSET) /* Control Register */ macro
254 writeb(XIIC_CR_TX_FIFO_RESET_MASK, priv->base + XIIC_CR_REG_OFFSET); in xiic_reinit()
257 writeb(XIIC_CR_ENABLE_DEVICE_MASK, priv->base + XIIC_CR_REG_OFFSET); in xiic_reinit()
329 writel(XIIC_CR_TX_FIFO_RESET_MASK, priv->base + XIIC_CR_REG_OFFSET); in xilinx_xiic_probe()
|
| /dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/drivers/i2c/ |
| H A D | xilinx_xiic.c | 32 #define XIIC_CR_REG_OFFSET (0x00+XIIC_REG_OFFSET) /* Control Register */ macro
254 writeb(XIIC_CR_TX_FIFO_RESET_MASK, priv->base + XIIC_CR_REG_OFFSET); in xiic_reinit()
257 writeb(XIIC_CR_ENABLE_DEVICE_MASK, priv->base + XIIC_CR_REG_OFFSET); in xiic_reinit()
329 writel(XIIC_CR_TX_FIFO_RESET_MASK, priv->base + XIIC_CR_REG_OFFSET); in xilinx_xiic_probe()
|
| /dports/sysutils/u-boot-rpi/u-boot-2021.07/drivers/i2c/ |
| H A D | xilinx_xiic.c | 32 #define XIIC_CR_REG_OFFSET (0x00+XIIC_REG_OFFSET) /* Control Register */ macro
254 writeb(XIIC_CR_TX_FIFO_RESET_MASK, priv->base + XIIC_CR_REG_OFFSET); in xiic_reinit()
257 writeb(XIIC_CR_ENABLE_DEVICE_MASK, priv->base + XIIC_CR_REG_OFFSET); in xiic_reinit()
329 writel(XIIC_CR_TX_FIFO_RESET_MASK, priv->base + XIIC_CR_REG_OFFSET); in xilinx_xiic_probe()
|
| /dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/drivers/i2c/ |
| H A D | xilinx_xiic.c | 32 #define XIIC_CR_REG_OFFSET (0x00+XIIC_REG_OFFSET) /* Control Register */ macro
254 writeb(XIIC_CR_TX_FIFO_RESET_MASK, priv->base + XIIC_CR_REG_OFFSET); in xiic_reinit()
257 writeb(XIIC_CR_ENABLE_DEVICE_MASK, priv->base + XIIC_CR_REG_OFFSET); in xiic_reinit()
329 writel(XIIC_CR_TX_FIFO_RESET_MASK, priv->base + XIIC_CR_REG_OFFSET); in xilinx_xiic_probe()
|
| /dports/sysutils/u-boot-nanopi-m1plus/u-boot-2021.07/drivers/i2c/ |
| H A D | xilinx_xiic.c | 32 #define XIIC_CR_REG_OFFSET (0x00+XIIC_REG_OFFSET) /* Control Register */ macro
254 writeb(XIIC_CR_TX_FIFO_RESET_MASK, priv->base + XIIC_CR_REG_OFFSET); in xiic_reinit()
257 writeb(XIIC_CR_ENABLE_DEVICE_MASK, priv->base + XIIC_CR_REG_OFFSET); in xiic_reinit()
329 writel(XIIC_CR_TX_FIFO_RESET_MASK, priv->base + XIIC_CR_REG_OFFSET); in xilinx_xiic_probe()
|
| /dports/sysutils/u-boot-wandboard/u-boot-2021.07/drivers/i2c/ |
| H A D | xilinx_xiic.c | 32 #define XIIC_CR_REG_OFFSET (0x00+XIIC_REG_OFFSET) /* Control Register */ macro
254 writeb(XIIC_CR_TX_FIFO_RESET_MASK, priv->base + XIIC_CR_REG_OFFSET); in xiic_reinit()
257 writeb(XIIC_CR_ENABLE_DEVICE_MASK, priv->base + XIIC_CR_REG_OFFSET); in xiic_reinit()
329 writel(XIIC_CR_TX_FIFO_RESET_MASK, priv->base + XIIC_CR_REG_OFFSET); in xilinx_xiic_probe()
|
| /dports/sysutils/u-boot-clearfog/u-boot-2021.07/drivers/i2c/ |
| H A D | xilinx_xiic.c | 32 #define XIIC_CR_REG_OFFSET (0x00+XIIC_REG_OFFSET) /* Control Register */ macro
254 writeb(XIIC_CR_TX_FIFO_RESET_MASK, priv->base + XIIC_CR_REG_OFFSET); in xiic_reinit()
257 writeb(XIIC_CR_ENABLE_DEVICE_MASK, priv->base + XIIC_CR_REG_OFFSET); in xiic_reinit()
329 writel(XIIC_CR_TX_FIFO_RESET_MASK, priv->base + XIIC_CR_REG_OFFSET); in xilinx_xiic_probe()
|
| /dports/sysutils/u-boot-cubieboard/u-boot-2021.07/drivers/i2c/ |
| H A D | xilinx_xiic.c | 32 #define XIIC_CR_REG_OFFSET (0x00+XIIC_REG_OFFSET) /* Control Register */ macro
254 writeb(XIIC_CR_TX_FIFO_RESET_MASK, priv->base + XIIC_CR_REG_OFFSET); in xiic_reinit()
257 writeb(XIIC_CR_ENABLE_DEVICE_MASK, priv->base + XIIC_CR_REG_OFFSET); in xiic_reinit()
329 writel(XIIC_CR_TX_FIFO_RESET_MASK, priv->base + XIIC_CR_REG_OFFSET); in xilinx_xiic_probe()
|
| /dports/sysutils/u-boot-pandaboard/u-boot-2021.07/drivers/i2c/ |
| H A D | xilinx_xiic.c | 32 #define XIIC_CR_REG_OFFSET (0x00+XIIC_REG_OFFSET) /* Control Register */ macro
254 writeb(XIIC_CR_TX_FIFO_RESET_MASK, priv->base + XIIC_CR_REG_OFFSET); in xiic_reinit()
257 writeb(XIIC_CR_ENABLE_DEVICE_MASK, priv->base + XIIC_CR_REG_OFFSET); in xiic_reinit()
329 writel(XIIC_CR_TX_FIFO_RESET_MASK, priv->base + XIIC_CR_REG_OFFSET); in xilinx_xiic_probe()
|
| /dports/sysutils/u-boot-orangepi-zero-plus/u-boot-2021.07/drivers/i2c/ |
| H A D | xilinx_xiic.c | 32 #define XIIC_CR_REG_OFFSET (0x00+XIIC_REG_OFFSET) /* Control Register */ macro
254 writeb(XIIC_CR_TX_FIFO_RESET_MASK, priv->base + XIIC_CR_REG_OFFSET); in xiic_reinit()
257 writeb(XIIC_CR_ENABLE_DEVICE_MASK, priv->base + XIIC_CR_REG_OFFSET); in xiic_reinit()
329 writel(XIIC_CR_TX_FIFO_RESET_MASK, priv->base + XIIC_CR_REG_OFFSET); in xilinx_xiic_probe()
|
| /dports/sysutils/u-boot-orangepi-zero/u-boot-2021.07/drivers/i2c/ |
| H A D | xilinx_xiic.c | 32 #define XIIC_CR_REG_OFFSET (0x00+XIIC_REG_OFFSET) /* Control Register */ macro
254 writeb(XIIC_CR_TX_FIFO_RESET_MASK, priv->base + XIIC_CR_REG_OFFSET); in xiic_reinit()
257 writeb(XIIC_CR_ENABLE_DEVICE_MASK, priv->base + XIIC_CR_REG_OFFSET); in xiic_reinit()
329 writel(XIIC_CR_TX_FIFO_RESET_MASK, priv->base + XIIC_CR_REG_OFFSET); in xilinx_xiic_probe()
|
| /dports/sysutils/u-boot-orangepi-r1/u-boot-2021.07/drivers/i2c/ |
| H A D | xilinx_xiic.c | 32 #define XIIC_CR_REG_OFFSET (0x00+XIIC_REG_OFFSET) /* Control Register */ macro
254 writeb(XIIC_CR_TX_FIFO_RESET_MASK, priv->base + XIIC_CR_REG_OFFSET); in xiic_reinit()
257 writeb(XIIC_CR_ENABLE_DEVICE_MASK, priv->base + XIIC_CR_REG_OFFSET); in xiic_reinit()
329 writel(XIIC_CR_TX_FIFO_RESET_MASK, priv->base + XIIC_CR_REG_OFFSET); in xilinx_xiic_probe()
|
| /dports/sysutils/u-boot-pine64/u-boot-2021.07/drivers/i2c/ |
| H A D | xilinx_xiic.c | 32 #define XIIC_CR_REG_OFFSET (0x00+XIIC_REG_OFFSET) /* Control Register */ macro
254 writeb(XIIC_CR_TX_FIFO_RESET_MASK, priv->base + XIIC_CR_REG_OFFSET); in xiic_reinit()
257 writeb(XIIC_CR_ENABLE_DEVICE_MASK, priv->base + XIIC_CR_REG_OFFSET); in xiic_reinit()
329 writel(XIIC_CR_TX_FIFO_RESET_MASK, priv->base + XIIC_CR_REG_OFFSET); in xilinx_xiic_probe()
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| /dports/sysutils/u-boot-pine-h64/u-boot-2021.07/drivers/i2c/ |
| H A D | xilinx_xiic.c | 32 #define XIIC_CR_REG_OFFSET (0x00+XIIC_REG_OFFSET) /* Control Register */ macro
254 writeb(XIIC_CR_TX_FIFO_RESET_MASK, priv->base + XIIC_CR_REG_OFFSET); in xiic_reinit()
257 writeb(XIIC_CR_ENABLE_DEVICE_MASK, priv->base + XIIC_CR_REG_OFFSET); in xiic_reinit()
329 writel(XIIC_CR_TX_FIFO_RESET_MASK, priv->base + XIIC_CR_REG_OFFSET); in xilinx_xiic_probe()
|
| /dports/sysutils/u-boot-pcduino3/u-boot-2021.07/drivers/i2c/ |
| H A D | xilinx_xiic.c | 32 #define XIIC_CR_REG_OFFSET (0x00+XIIC_REG_OFFSET) /* Control Register */ macro
254 writeb(XIIC_CR_TX_FIFO_RESET_MASK, priv->base + XIIC_CR_REG_OFFSET); in xiic_reinit()
257 writeb(XIIC_CR_ENABLE_DEVICE_MASK, priv->base + XIIC_CR_REG_OFFSET); in xiic_reinit()
329 writel(XIIC_CR_TX_FIFO_RESET_MASK, priv->base + XIIC_CR_REG_OFFSET); in xilinx_xiic_probe()
|