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Searched refs:ZBIT16 (Results 1 – 16 of 16) sorted by relevance

/dports/devel/avr-gdb/gdb-7.3.1/sim/arm/
H A Diwmmxt.c72 #define ZBIT16(x) (((x) & 0xffff) == 0) macro
1581 SIMD16_SET (psr, ZBIT16 (s), SIMD_ZBIT, i); in WAVG2()
1635 SIMD16_SET (psr, ZBIT16 (s), SIMD_ZBIT, i); in WCMPEQ()
2611 SIMD16_SET (psr, ZBIT16 (s), SIMD_ZBIT, i); in WPACK()
2684 SIMD16_SET (psr, ZBIT16 (s), SIMD_ZBIT, i); in WROR()
2782 SIMD16_SET (psr, ZBIT16 (s), SIMD_ZBIT, i); in WSHUFH()
2821 SIMD16_SET (psr, ZBIT16 (s), SIMD_ZBIT, i); in WSLL()
2896 SIMD16_SET (psr, ZBIT16 (s), SIMD_ZBIT, i); in WSRA()
2968 SIMD16_SET (psr, ZBIT16 (s), SIMD_ZBIT, i); in WSRL()
3270 SIMD16_SET (psr, ZBIT16 (s), SIMD_ZBIT, i); in WUNPCKEH()
[all …]
/dports/devel/gdb761/gdb-7.6.1/sim/arm/
H A Diwmmxt.c71 #define ZBIT16(x) (((x) & 0xffff) == 0) macro
1580 SIMD16_SET (psr, ZBIT16 (s), SIMD_ZBIT, i); in WAVG2()
1634 SIMD16_SET (psr, ZBIT16 (s), SIMD_ZBIT, i); in WCMPEQ()
2613 SIMD16_SET (psr, ZBIT16 (s), SIMD_ZBIT, i); in WPACK()
2686 SIMD16_SET (psr, ZBIT16 (s), SIMD_ZBIT, i); in WROR()
2784 SIMD16_SET (psr, ZBIT16 (s), SIMD_ZBIT, i); in WSHUFH()
2823 SIMD16_SET (psr, ZBIT16 (s), SIMD_ZBIT, i); in WSLL()
2898 SIMD16_SET (psr, ZBIT16 (s), SIMD_ZBIT, i); in WSRA()
2970 SIMD16_SET (psr, ZBIT16 (s), SIMD_ZBIT, i); in WSRL()
3272 SIMD16_SET (psr, ZBIT16 (s), SIMD_ZBIT, i); in WUNPCKEH()
[all …]
/dports/devel/zpu-binutils/zpu-toolchain-1.0/toolchain/gdb/sim/arm/
H A Diwmmxt.c70 #define ZBIT16(x) (((x) & 0xffff) == 0) macro
1579 SIMD16_SET (psr, ZBIT16 (s), SIMD_ZBIT, i); in WAVG2()
1633 SIMD16_SET (psr, ZBIT16 (s), SIMD_ZBIT, i); in WCMPEQ()
2609 SIMD16_SET (psr, ZBIT16 (s), SIMD_ZBIT, i); in WPACK()
2682 SIMD16_SET (psr, ZBIT16 (s), SIMD_ZBIT, i); in WROR()
2780 SIMD16_SET (psr, ZBIT16 (s), SIMD_ZBIT, i); in WSHUFH()
2819 SIMD16_SET (psr, ZBIT16 (s), SIMD_ZBIT, i); in WSLL()
2894 SIMD16_SET (psr, ZBIT16 (s), SIMD_ZBIT, i); in WSRA()
2966 SIMD16_SET (psr, ZBIT16 (s), SIMD_ZBIT, i); in WSRL()
3268 SIMD16_SET (psr, ZBIT16 (s), SIMD_ZBIT, i); in WUNPCKEH()
[all …]
/dports/devel/zpu-gcc/zpu-toolchain-1.0/toolchain/gdb/sim/arm/
H A Diwmmxt.c70 #define ZBIT16(x) (((x) & 0xffff) == 0) macro
1579 SIMD16_SET (psr, ZBIT16 (s), SIMD_ZBIT, i); in WAVG2()
1633 SIMD16_SET (psr, ZBIT16 (s), SIMD_ZBIT, i); in WCMPEQ()
2609 SIMD16_SET (psr, ZBIT16 (s), SIMD_ZBIT, i); in WPACK()
2682 SIMD16_SET (psr, ZBIT16 (s), SIMD_ZBIT, i); in WROR()
2780 SIMD16_SET (psr, ZBIT16 (s), SIMD_ZBIT, i); in WSHUFH()
2819 SIMD16_SET (psr, ZBIT16 (s), SIMD_ZBIT, i); in WSLL()
2894 SIMD16_SET (psr, ZBIT16 (s), SIMD_ZBIT, i); in WSRA()
2966 SIMD16_SET (psr, ZBIT16 (s), SIMD_ZBIT, i); in WSRL()
3268 SIMD16_SET (psr, ZBIT16 (s), SIMD_ZBIT, i); in WUNPCKEH()
[all …]
/dports/emulators/qemu-utils/qemu-4.2.1/target/arm/
H A Diwmmxt_helper.c45 #define ZBIT16(x) (((x) & 0xffff) == 0) macro
155 SIMD16_SET(ZBIT16((x) & 0xffff), SIMD_ZBIT, i)
359 SIMD16_SET(ZBIT16((a >> 0) & 0xffff), SIMD_ZBIT, 0) | \
360 SIMD16_SET(ZBIT16((a >> 16) & 0xffff), SIMD_ZBIT, 1) | \
361 SIMD16_SET(ZBIT16((a >> 32) & 0xffff), SIMD_ZBIT, 2) | \
362 SIMD16_SET(ZBIT16((a >> 48) & 0xffff), SIMD_ZBIT, 3); \
/dports/emulators/x49gp/x49gp/x49gp-code/qemu/qemu-git/target-arm/
H A Diwmmxt_helper.c47 #define ZBIT16(x) (((x) & 0xffff) == 0) macro
157 SIMD16_SET(ZBIT16((x) & 0xffff), SIMD_ZBIT, i)
361 SIMD16_SET(ZBIT16((a >> 0) & 0xffff), SIMD_ZBIT, 0) | \
362 SIMD16_SET(ZBIT16((a >> 16) & 0xffff), SIMD_ZBIT, 1) | \
363 SIMD16_SET(ZBIT16((a >> 32) & 0xffff), SIMD_ZBIT, 2) | \
364 SIMD16_SET(ZBIT16((a >> 48) & 0xffff), SIMD_ZBIT, 3); \
/dports/emulators/py-unicorn/unicorn-1.0.2/qemu/target-arm/
H A Diwmmxt_helper.c47 #define ZBIT16(x) (((x) & 0xffff) == 0) macro
157 SIMD16_SET(ZBIT16((x) & 0xffff), SIMD_ZBIT, i)
361 SIMD16_SET(ZBIT16((a >> 0) & 0xffff), SIMD_ZBIT, 0) | \
362 SIMD16_SET(ZBIT16((a >> 16) & 0xffff), SIMD_ZBIT, 1) | \
363 SIMD16_SET(ZBIT16((a >> 32) & 0xffff), SIMD_ZBIT, 2) | \
364 SIMD16_SET(ZBIT16((a >> 48) & 0xffff), SIMD_ZBIT, 3); \
/dports/emulators/qemu5/qemu-5.2.0/target/arm/
H A Diwmmxt_helper.c45 #define ZBIT16(x) (((x) & 0xffff) == 0) macro
155 SIMD16_SET(ZBIT16((x) & 0xffff), SIMD_ZBIT, i)
359 SIMD16_SET(ZBIT16((a >> 0) & 0xffff), SIMD_ZBIT, 0) | \
360 SIMD16_SET(ZBIT16((a >> 16) & 0xffff), SIMD_ZBIT, 1) | \
361 SIMD16_SET(ZBIT16((a >> 32) & 0xffff), SIMD_ZBIT, 2) | \
362 SIMD16_SET(ZBIT16((a >> 48) & 0xffff), SIMD_ZBIT, 3); \
/dports/emulators/qemu-guest-agent/qemu-5.0.1/target/arm/
H A Diwmmxt_helper.c45 #define ZBIT16(x) (((x) & 0xffff) == 0) macro
155 SIMD16_SET(ZBIT16((x) & 0xffff), SIMD_ZBIT, i)
359 SIMD16_SET(ZBIT16((a >> 0) & 0xffff), SIMD_ZBIT, 0) | \
360 SIMD16_SET(ZBIT16((a >> 16) & 0xffff), SIMD_ZBIT, 1) | \
361 SIMD16_SET(ZBIT16((a >> 32) & 0xffff), SIMD_ZBIT, 2) | \
362 SIMD16_SET(ZBIT16((a >> 48) & 0xffff), SIMD_ZBIT, 3); \
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/target/arm/
H A Diwmmxt_helper.c45 #define ZBIT16(x) (((x) & 0xffff) == 0) macro
155 SIMD16_SET(ZBIT16((x) & 0xffff), SIMD_ZBIT, i)
359 SIMD16_SET(ZBIT16((a >> 0) & 0xffff), SIMD_ZBIT, 0) | \
360 SIMD16_SET(ZBIT16((a >> 16) & 0xffff), SIMD_ZBIT, 1) | \
361 SIMD16_SET(ZBIT16((a >> 32) & 0xffff), SIMD_ZBIT, 2) | \
362 SIMD16_SET(ZBIT16((a >> 48) & 0xffff), SIMD_ZBIT, 3); \
/dports/emulators/qemu42/qemu-4.2.1/target/arm/
H A Diwmmxt_helper.c45 #define ZBIT16(x) (((x) & 0xffff) == 0) macro
155 SIMD16_SET(ZBIT16((x) & 0xffff), SIMD_ZBIT, i)
359 SIMD16_SET(ZBIT16((a >> 0) & 0xffff), SIMD_ZBIT, 0) | \
360 SIMD16_SET(ZBIT16((a >> 16) & 0xffff), SIMD_ZBIT, 1) | \
361 SIMD16_SET(ZBIT16((a >> 32) & 0xffff), SIMD_ZBIT, 2) | \
362 SIMD16_SET(ZBIT16((a >> 48) & 0xffff), SIMD_ZBIT, 3); \
/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/target/arm/
H A Diwmmxt_helper.c45 #define ZBIT16(x) (((x) & 0xffff) == 0) macro
155 SIMD16_SET(ZBIT16((x) & 0xffff), SIMD_ZBIT, i)
359 SIMD16_SET(ZBIT16((a >> 0) & 0xffff), SIMD_ZBIT, 0) | \
360 SIMD16_SET(ZBIT16((a >> 16) & 0xffff), SIMD_ZBIT, 1) | \
361 SIMD16_SET(ZBIT16((a >> 32) & 0xffff), SIMD_ZBIT, 2) | \
362 SIMD16_SET(ZBIT16((a >> 48) & 0xffff), SIMD_ZBIT, 3); \
/dports/emulators/qemu/qemu-6.2.0/target/arm/
H A Diwmmxt_helper.c45 #define ZBIT16(x) (((x) & 0xffff) == 0) macro
155 SIMD16_SET(ZBIT16((x) & 0xffff), SIMD_ZBIT, i)
359 SIMD16_SET(ZBIT16((a >> 0) & 0xffff), SIMD_ZBIT, 0) | \
360 SIMD16_SET(ZBIT16((a >> 16) & 0xffff), SIMD_ZBIT, 1) | \
361 SIMD16_SET(ZBIT16((a >> 32) & 0xffff), SIMD_ZBIT, 2) | \
362 SIMD16_SET(ZBIT16((a >> 48) & 0xffff), SIMD_ZBIT, 3); \
/dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/target/arm/
H A Diwmmxt_helper.c45 #define ZBIT16(x) (((x) & 0xffff) == 0) macro
155 SIMD16_SET(ZBIT16((x) & 0xffff), SIMD_ZBIT, i)
359 SIMD16_SET(ZBIT16((a >> 0) & 0xffff), SIMD_ZBIT, 0) | \
360 SIMD16_SET(ZBIT16((a >> 16) & 0xffff), SIMD_ZBIT, 1) | \
361 SIMD16_SET(ZBIT16((a >> 32) & 0xffff), SIMD_ZBIT, 2) | \
362 SIMD16_SET(ZBIT16((a >> 48) & 0xffff), SIMD_ZBIT, 3); \
/dports/emulators/qemu60/qemu-6.0.0/target/arm/
H A Diwmmxt_helper.c45 #define ZBIT16(x) (((x) & 0xffff) == 0) macro
155 SIMD16_SET(ZBIT16((x) & 0xffff), SIMD_ZBIT, i)
359 SIMD16_SET(ZBIT16((a >> 0) & 0xffff), SIMD_ZBIT, 0) | \
360 SIMD16_SET(ZBIT16((a >> 16) & 0xffff), SIMD_ZBIT, 1) | \
361 SIMD16_SET(ZBIT16((a >> 32) & 0xffff), SIMD_ZBIT, 2) | \
362 SIMD16_SET(ZBIT16((a >> 48) & 0xffff), SIMD_ZBIT, 3); \
/dports/emulators/unicorn/unicorn-1.0.2/qemu/target-arm/
H A Diwmmxt_helper.c47 #define ZBIT16(x) (((x) & 0xffff) == 0) macro
157 SIMD16_SET(ZBIT16((x) & 0xffff), SIMD_ZBIT, i)
361 SIMD16_SET(ZBIT16((a >> 0) & 0xffff), SIMD_ZBIT, 0) | \
362 SIMD16_SET(ZBIT16((a >> 16) & 0xffff), SIMD_ZBIT, 1) | \
363 SIMD16_SET(ZBIT16((a >> 32) & 0xffff), SIMD_ZBIT, 2) | \
364 SIMD16_SET(ZBIT16((a >> 48) & 0xffff), SIMD_ZBIT, 3); \