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Searched refs:ZeroExtend (Results 1 – 25 of 403) sorted by relevance

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/dports/emulators/yuzu/yuzu-0b47f7a46/externals/dynarmic/src/frontend/A64/translate/impl/
H A Dsimd_copy.cpp12 const size_t size = Common::LowestSetBit(imm5.ZeroExtend()); in DUP_elt_1()
17 const size_t index = imm5.ZeroExtend<size_t>() >> (size + 1); in DUP_elt_1()
29 const size_t size = Common::LowestSetBit(imm5.ZeroExtend()); in DUP_elt_2()
38 const size_t index = imm5.ZeroExtend<size_t>() >> (size + 1); in DUP_elt_2()
51 const size_t size = Common::LowestSetBit(imm5.ZeroExtend()); in DUP_gen()
73 const size_t size = Common::LowestSetBit(imm5.ZeroExtend()); in SMOV()
83 const size_t index = imm5.ZeroExtend<size_t>() >> (size + 1); in SMOV()
96 const size_t size = Common::LowestSetBit(imm5.ZeroExtend()); in UMOV()
117 X(datasize, Rd, ZeroExtend(elem, datasize)); in UMOV()
123 const size_t size = Common::LowestSetBit(imm5.ZeroExtend()); in INS_gen()
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H A Ddata_processing_addsub.cpp12 switch (shift.ZeroExtend()) { in ADD_imm()
14 imm = imm12.ZeroExtend<u64>(); in ADD_imm()
17 imm = imm12.ZeroExtend<u64>() << 12; in ADD_imm()
39 switch (shift.ZeroExtend()) { in ADDS_imm()
41 imm = imm12.ZeroExtend<u64>(); in ADDS_imm()
44 imm = imm12.ZeroExtend<u64>() << 12; in ADDS_imm()
63 switch (shift.ZeroExtend()) { in SUB_imm()
65 imm = imm12.ZeroExtend<u64>(); in SUB_imm()
68 imm = imm12.ZeroExtend<u64>() << 12; in SUB_imm()
90 switch (shift.ZeroExtend()) { in SUBS_imm()
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H A Dload_store_exclusive.cpp67 v.X(regsize, Rt, v.ZeroExtend(data, regsize)); in ExclusiveSharedDecodeAndOperation()
80 const size_t size = sz.ZeroExtend<size_t>(); in STXR()
88 const size_t size = sz.ZeroExtend<size_t>(); in STLXR()
96 const size_t size = concatenate(Imm<1>{1}, sz).ZeroExtend<size_t>(); in STXP()
112 const size_t size = sz.ZeroExtend<size_t>(); in LDXR()
120 const size_t size = sz.ZeroExtend<size_t>(); in LDAXR()
171 v.X(regsize, Rt, v.ZeroExtend(data, regsize)); in OrderedSharedDecodeAndOperation()
182 const size_t size = sz.ZeroExtend<size_t>(); in STLLR()
189 const size_t size = sz.ZeroExtend<size_t>(); in STLR()
196 const size_t size = sz.ZeroExtend<size_t>(); in LDLAR()
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H A Dload_store_single_structure.cpp21 index = Q << 3 | S << 2 | size.ZeroExtend(); in SharedDecodeAndOperation()
47 scale = size.ZeroExtend(); in SharedDecodeAndOperation()
108 Imm<3>{upper_opcode.ZeroExtend() << 1}, size, Rn, Vt); in LD1_sngl_1()
113 Imm<3>{upper_opcode.ZeroExtend() << 1}, size, Rn, Vt); in LD1_sngl_2()
128 Imm<3>{upper_opcode.ZeroExtend() << 1}, size, Rn, Vt); in LD2_sngl_1()
133 Imm<3>{upper_opcode.ZeroExtend() << 1}, size, Rn, Vt); in LD2_sngl_2()
148 Imm<3>{(upper_opcode.ZeroExtend() << 1) | 1}, size, Rn, Vt); in LD3_sngl_1()
188 Imm<3>{upper_opcode.ZeroExtend() << 1}, size, Rn, Vt); in ST1_sngl_1()
193 Imm<3>{upper_opcode.ZeroExtend() << 1}, size, Rn, Vt); in ST1_sngl_2()
198 Imm<3>{upper_opcode.ZeroExtend() << 1}, size, Rn, Vt); in ST2_sngl_1()
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H A Dmove_wide.cpp16 const size_t pos = hw.ZeroExtend<size_t>() << 4; in MOVN()
18 u64 value = imm16.ZeroExtend<u64>() << pos; in MOVN()
32 const size_t pos = hw.ZeroExtend<size_t>() << 4; in MOVZ()
34 const u64 value = imm16.ZeroExtend<u64>() << pos; in MOVZ()
47 const size_t pos = hw.ZeroExtend<size_t>() << 4; in MOVK()
50 const u64 value = imm16.ZeroExtend<u64>() << pos; in MOVK()
H A Dsimd_scalar_x_indexed_element.cpp13 return {concatenate(H, L, M).ZeroExtend(), Vmlo.ZeroExtend<Vec>()}; in Combine()
16 return {concatenate(H, L).ZeroExtend(), concatenate(M, Vmlo).ZeroExtend<Vec>()}; in Combine()
33 const size_t index = sz ? H.ZeroExtend() : concatenate(H, L).ZeroExtend(); in MultiplyByElement()
34 const Vec Vm = concatenate(M, Vmlo).ZeroExtend<Vec>(); in MultiplyByElement()
65 const size_t index = concatenate(H, L, M).ZeroExtend(); in MultiplyByElementHalfPrecision()
67 const auto Vm = Vmlo.ZeroExtend<Vec>(); in MultiplyByElementHalfPrecision()
125 const size_t esize = 8 << size.ZeroExtend(); in SQDMULH_elt_1()
143 const size_t esize = 8 << size.ZeroExtend(); in SQRDMULH_elt_1()
161 const size_t esize = 8 << size.ZeroExtend(); in SQDMULL_elt_1()
/dports/emulators/citra/citra-ac98458e0/externals/dynarmic/src/frontend/A64/translate/impl/
H A Dsimd_copy.cpp12 const size_t size = Common::LowestSetBit(imm5.ZeroExtend()); in DUP_elt_1()
17 const size_t index = imm5.ZeroExtend<size_t>() >> (size + 1); in DUP_elt_1()
29 const size_t size = Common::LowestSetBit(imm5.ZeroExtend()); in DUP_elt_2()
38 const size_t index = imm5.ZeroExtend<size_t>() >> (size + 1); in DUP_elt_2()
51 const size_t size = Common::LowestSetBit(imm5.ZeroExtend()); in DUP_gen()
73 const size_t size = Common::LowestSetBit(imm5.ZeroExtend()); in SMOV()
83 const size_t index = imm5.ZeroExtend<size_t>() >> (size + 1); in SMOV()
96 const size_t size = Common::LowestSetBit(imm5.ZeroExtend()); in UMOV()
117 X(datasize, Rd, ZeroExtend(elem, datasize)); in UMOV()
123 const size_t size = Common::LowestSetBit(imm5.ZeroExtend()); in INS_gen()
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H A Ddata_processing_addsub.cpp12 switch (shift.ZeroExtend()) { in ADD_imm()
14 imm = imm12.ZeroExtend<u64>(); in ADD_imm()
17 imm = imm12.ZeroExtend<u64>() << 12; in ADD_imm()
39 switch (shift.ZeroExtend()) { in ADDS_imm()
41 imm = imm12.ZeroExtend<u64>(); in ADDS_imm()
44 imm = imm12.ZeroExtend<u64>() << 12; in ADDS_imm()
63 switch (shift.ZeroExtend()) { in SUB_imm()
65 imm = imm12.ZeroExtend<u64>(); in SUB_imm()
68 imm = imm12.ZeroExtend<u64>() << 12; in SUB_imm()
90 switch (shift.ZeroExtend()) { in SUBS_imm()
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H A Dload_store_exclusive.cpp67 v.X(regsize, Rt, v.ZeroExtend(data, regsize)); in ExclusiveSharedDecodeAndOperation()
80 const size_t size = sz.ZeroExtend<size_t>(); in STXR()
88 const size_t size = sz.ZeroExtend<size_t>(); in STLXR()
96 const size_t size = concatenate(Imm<1>{1}, sz).ZeroExtend<size_t>(); in STXP()
112 const size_t size = sz.ZeroExtend<size_t>(); in LDXR()
120 const size_t size = sz.ZeroExtend<size_t>(); in LDAXR()
171 v.X(regsize, Rt, v.ZeroExtend(data, regsize)); in OrderedSharedDecodeAndOperation()
182 const size_t size = sz.ZeroExtend<size_t>(); in STLLR()
189 const size_t size = sz.ZeroExtend<size_t>(); in STLR()
196 const size_t size = sz.ZeroExtend<size_t>(); in LDLAR()
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H A Dload_store_single_structure.cpp21 index = Q << 3 | S << 2 | size.ZeroExtend(); in SharedDecodeAndOperation()
47 scale = size.ZeroExtend(); in SharedDecodeAndOperation()
108 Imm<3>{upper_opcode.ZeroExtend() << 1}, size, Rn, Vt); in LD1_sngl_1()
113 Imm<3>{upper_opcode.ZeroExtend() << 1}, size, Rn, Vt); in LD1_sngl_2()
128 Imm<3>{upper_opcode.ZeroExtend() << 1}, size, Rn, Vt); in LD2_sngl_1()
133 Imm<3>{upper_opcode.ZeroExtend() << 1}, size, Rn, Vt); in LD2_sngl_2()
148 Imm<3>{(upper_opcode.ZeroExtend() << 1) | 1}, size, Rn, Vt); in LD3_sngl_1()
188 Imm<3>{upper_opcode.ZeroExtend() << 1}, size, Rn, Vt); in ST1_sngl_1()
193 Imm<3>{upper_opcode.ZeroExtend() << 1}, size, Rn, Vt); in ST1_sngl_2()
198 Imm<3>{upper_opcode.ZeroExtend() << 1}, size, Rn, Vt); in ST2_sngl_1()
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H A Dmove_wide.cpp16 const size_t pos = hw.ZeroExtend<size_t>() << 4; in MOVN()
18 u64 value = imm16.ZeroExtend<u64>() << pos; in MOVN()
32 const size_t pos = hw.ZeroExtend<size_t>() << 4; in MOVZ()
34 const u64 value = imm16.ZeroExtend<u64>() << pos; in MOVZ()
47 const size_t pos = hw.ZeroExtend<size_t>() << 4; in MOVK()
50 const u64 value = imm16.ZeroExtend<u64>() << pos; in MOVK()
H A Dsimd_scalar_x_indexed_element.cpp13 return {concatenate(H, L, M).ZeroExtend(), Vmlo.ZeroExtend<Vec>()}; in Combine()
16 return {concatenate(H, L).ZeroExtend(), concatenate(M, Vmlo).ZeroExtend<Vec>()}; in Combine()
33 const size_t index = sz ? H.ZeroExtend() : concatenate(H, L).ZeroExtend(); in MultiplyByElement()
34 const Vec Vm = concatenate(M, Vmlo).ZeroExtend<Vec>(); in MultiplyByElement()
65 const size_t index = concatenate(H, L, M).ZeroExtend(); in MultiplyByElementHalfPrecision()
67 const auto Vm = Vmlo.ZeroExtend<Vec>(); in MultiplyByElementHalfPrecision()
125 const size_t esize = 8 << size.ZeroExtend(); in SQDMULH_elt_1()
143 const size_t esize = 8 << size.ZeroExtend(); in SQRDMULH_elt_1()
161 const size_t esize = 8 << size.ZeroExtend(); in SQDMULL_elt_1()
/dports/emulators/citra-qt5/citra-ac98458e0/externals/dynarmic/src/frontend/A64/translate/impl/
H A Dsimd_copy.cpp12 const size_t size = Common::LowestSetBit(imm5.ZeroExtend()); in DUP_elt_1()
17 const size_t index = imm5.ZeroExtend<size_t>() >> (size + 1); in DUP_elt_1()
29 const size_t size = Common::LowestSetBit(imm5.ZeroExtend()); in DUP_elt_2()
38 const size_t index = imm5.ZeroExtend<size_t>() >> (size + 1); in DUP_elt_2()
51 const size_t size = Common::LowestSetBit(imm5.ZeroExtend()); in DUP_gen()
73 const size_t size = Common::LowestSetBit(imm5.ZeroExtend()); in SMOV()
83 const size_t index = imm5.ZeroExtend<size_t>() >> (size + 1); in SMOV()
96 const size_t size = Common::LowestSetBit(imm5.ZeroExtend()); in UMOV()
117 X(datasize, Rd, ZeroExtend(elem, datasize)); in UMOV()
123 const size_t size = Common::LowestSetBit(imm5.ZeroExtend()); in INS_gen()
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H A Ddata_processing_addsub.cpp12 switch (shift.ZeroExtend()) { in ADD_imm()
14 imm = imm12.ZeroExtend<u64>(); in ADD_imm()
17 imm = imm12.ZeroExtend<u64>() << 12; in ADD_imm()
39 switch (shift.ZeroExtend()) { in ADDS_imm()
41 imm = imm12.ZeroExtend<u64>(); in ADDS_imm()
44 imm = imm12.ZeroExtend<u64>() << 12; in ADDS_imm()
63 switch (shift.ZeroExtend()) { in SUB_imm()
65 imm = imm12.ZeroExtend<u64>(); in SUB_imm()
68 imm = imm12.ZeroExtend<u64>() << 12; in SUB_imm()
90 switch (shift.ZeroExtend()) { in SUBS_imm()
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H A Dload_store_exclusive.cpp67 v.X(regsize, Rt, v.ZeroExtend(data, regsize)); in ExclusiveSharedDecodeAndOperation()
80 const size_t size = sz.ZeroExtend<size_t>(); in STXR()
88 const size_t size = sz.ZeroExtend<size_t>(); in STLXR()
96 const size_t size = concatenate(Imm<1>{1}, sz).ZeroExtend<size_t>(); in STXP()
112 const size_t size = sz.ZeroExtend<size_t>(); in LDXR()
120 const size_t size = sz.ZeroExtend<size_t>(); in LDAXR()
171 v.X(regsize, Rt, v.ZeroExtend(data, regsize)); in OrderedSharedDecodeAndOperation()
182 const size_t size = sz.ZeroExtend<size_t>(); in STLLR()
189 const size_t size = sz.ZeroExtend<size_t>(); in STLR()
196 const size_t size = sz.ZeroExtend<size_t>(); in LDLAR()
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H A Dload_store_single_structure.cpp21 index = Q << 3 | S << 2 | size.ZeroExtend(); in SharedDecodeAndOperation()
47 scale = size.ZeroExtend(); in SharedDecodeAndOperation()
108 Imm<3>{upper_opcode.ZeroExtend() << 1}, size, Rn, Vt); in LD1_sngl_1()
113 Imm<3>{upper_opcode.ZeroExtend() << 1}, size, Rn, Vt); in LD1_sngl_2()
128 Imm<3>{upper_opcode.ZeroExtend() << 1}, size, Rn, Vt); in LD2_sngl_1()
133 Imm<3>{upper_opcode.ZeroExtend() << 1}, size, Rn, Vt); in LD2_sngl_2()
148 Imm<3>{(upper_opcode.ZeroExtend() << 1) | 1}, size, Rn, Vt); in LD3_sngl_1()
188 Imm<3>{upper_opcode.ZeroExtend() << 1}, size, Rn, Vt); in ST1_sngl_1()
193 Imm<3>{upper_opcode.ZeroExtend() << 1}, size, Rn, Vt); in ST1_sngl_2()
198 Imm<3>{upper_opcode.ZeroExtend() << 1}, size, Rn, Vt); in ST2_sngl_1()
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H A Dmove_wide.cpp16 const size_t pos = hw.ZeroExtend<size_t>() << 4; in MOVN()
18 u64 value = imm16.ZeroExtend<u64>() << pos; in MOVN()
32 const size_t pos = hw.ZeroExtend<size_t>() << 4; in MOVZ()
34 const u64 value = imm16.ZeroExtend<u64>() << pos; in MOVZ()
47 const size_t pos = hw.ZeroExtend<size_t>() << 4; in MOVK()
50 const u64 value = imm16.ZeroExtend<u64>() << pos; in MOVK()
H A Dsimd_scalar_x_indexed_element.cpp13 return {concatenate(H, L, M).ZeroExtend(), Vmlo.ZeroExtend<Vec>()}; in Combine()
16 return {concatenate(H, L).ZeroExtend(), concatenate(M, Vmlo).ZeroExtend<Vec>()}; in Combine()
33 const size_t index = sz ? H.ZeroExtend() : concatenate(H, L).ZeroExtend(); in MultiplyByElement()
34 const Vec Vm = concatenate(M, Vmlo).ZeroExtend<Vec>(); in MultiplyByElement()
65 const size_t index = concatenate(H, L, M).ZeroExtend(); in MultiplyByElementHalfPrecision()
67 const auto Vm = Vmlo.ZeroExtend<Vec>(); in MultiplyByElementHalfPrecision()
125 const size_t esize = 8 << size.ZeroExtend(); in SQDMULH_elt_1()
143 const size_t esize = 8 << size.ZeroExtend(); in SQRDMULH_elt_1()
161 const size_t esize = 8 << size.ZeroExtend(); in SQDMULL_elt_1()
/dports/emulators/yuzu/yuzu-0b47f7a46/externals/dynarmic/src/frontend/
H A Dimm.cpp16 return Common::Replicate<u64>(imm8.ZeroExtend<u64>(), 32); in AdvSIMDExpandImm()
18 return Common::Replicate<u64>(imm8.ZeroExtend<u64>() << 8, 32); in AdvSIMDExpandImm()
20 return Common::Replicate<u64>(imm8.ZeroExtend<u64>() << 16, 32); in AdvSIMDExpandImm()
22 return Common::Replicate<u64>(imm8.ZeroExtend<u64>() << 24, 32); in AdvSIMDExpandImm()
24 return Common::Replicate<u64>(imm8.ZeroExtend<u64>(), 16); in AdvSIMDExpandImm()
26 return Common::Replicate<u64>(imm8.ZeroExtend<u64>() << 8, 16); in AdvSIMDExpandImm()
29 return Common::Replicate<u64>((imm8.ZeroExtend<u64>() << 8) | Common::Ones<u64>(8), 32); in AdvSIMDExpandImm()
31 return Common::Replicate<u64>((imm8.ZeroExtend<u64>() << 16) | Common::Ones<u64>(16), 32); in AdvSIMDExpandImm()
34 return Common::Replicate<u64>(imm8.ZeroExtend<u64>(), 8); in AdvSIMDExpandImm()
/dports/emulators/citra-qt5/citra-ac98458e0/externals/dynarmic/src/frontend/
H A Dimm.cpp16 return Common::Replicate<u64>(imm8.ZeroExtend<u64>(), 32); in AdvSIMDExpandImm()
18 return Common::Replicate<u64>(imm8.ZeroExtend<u64>() << 8, 32); in AdvSIMDExpandImm()
20 return Common::Replicate<u64>(imm8.ZeroExtend<u64>() << 16, 32); in AdvSIMDExpandImm()
22 return Common::Replicate<u64>(imm8.ZeroExtend<u64>() << 24, 32); in AdvSIMDExpandImm()
24 return Common::Replicate<u64>(imm8.ZeroExtend<u64>(), 16); in AdvSIMDExpandImm()
26 return Common::Replicate<u64>(imm8.ZeroExtend<u64>() << 8, 16); in AdvSIMDExpandImm()
29 return Common::Replicate<u64>((imm8.ZeroExtend<u64>() << 8) | Common::Ones<u64>(8), 32); in AdvSIMDExpandImm()
31 return Common::Replicate<u64>((imm8.ZeroExtend<u64>() << 16) | Common::Ones<u64>(16), 32); in AdvSIMDExpandImm()
34 return Common::Replicate<u64>(imm8.ZeroExtend<u64>(), 8); in AdvSIMDExpandImm()
/dports/emulators/citra/citra-ac98458e0/externals/dynarmic/src/frontend/
H A Dimm.cpp16 return Common::Replicate<u64>(imm8.ZeroExtend<u64>(), 32); in AdvSIMDExpandImm()
18 return Common::Replicate<u64>(imm8.ZeroExtend<u64>() << 8, 32); in AdvSIMDExpandImm()
20 return Common::Replicate<u64>(imm8.ZeroExtend<u64>() << 16, 32); in AdvSIMDExpandImm()
22 return Common::Replicate<u64>(imm8.ZeroExtend<u64>() << 24, 32); in AdvSIMDExpandImm()
24 return Common::Replicate<u64>(imm8.ZeroExtend<u64>(), 16); in AdvSIMDExpandImm()
26 return Common::Replicate<u64>(imm8.ZeroExtend<u64>() << 8, 16); in AdvSIMDExpandImm()
29 return Common::Replicate<u64>((imm8.ZeroExtend<u64>() << 8) | Common::Ones<u64>(8), 32); in AdvSIMDExpandImm()
31 return Common::Replicate<u64>((imm8.ZeroExtend<u64>() << 16) | Common::Ones<u64>(16), 32); in AdvSIMDExpandImm()
34 return Common::Replicate<u64>(imm8.ZeroExtend<u64>(), 8); in AdvSIMDExpandImm()
/dports/emulators/yuzu/yuzu-0b47f7a46/externals/dynarmic/src/frontend/A32/disassembler/
H A Ddisassembler_thumb.cpp152 const u32 imm32 = imm8.ZeroExtend() << 2; in thumb16_LDR_literal()
189 const u32 imm32 = imm5.ZeroExtend() << 2; in thumb16_STR_imm_t1()
194 const u32 imm32 = imm5.ZeroExtend() << 2; in thumb16_LDR_imm_t1()
199 const u32 imm32 = imm5.ZeroExtend(); in thumb16_STRB_imm()
204 const u32 imm32 = imm5.ZeroExtend(); in thumb16_LDRB_imm()
209 const u32 imm32 = imm5.ZeroExtend() << 1; in thumb16_STRH_imm()
214 const u32 imm32 = imm5.ZeroExtend() << 1; in thumb16_LDRH_imm()
219 const u32 imm32 = imm8.ZeroExtend() << 2; in thumb16_STR_imm_t2()
224 const u32 imm32 = imm8.ZeroExtend() << 2; in thumb16_LDR_imm_t2()
229 const u32 imm32 = imm8.ZeroExtend() << 2; in thumb16_ADR()
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/dports/emulators/citra-qt5/citra-ac98458e0/externals/dynarmic/src/frontend/A32/disassembler/
H A Ddisassembler_thumb.cpp152 const u32 imm32 = imm8.ZeroExtend() << 2; in thumb16_LDR_literal()
189 const u32 imm32 = imm5.ZeroExtend() << 2; in thumb16_STR_imm_t1()
194 const u32 imm32 = imm5.ZeroExtend() << 2; in thumb16_LDR_imm_t1()
199 const u32 imm32 = imm5.ZeroExtend(); in thumb16_STRB_imm()
204 const u32 imm32 = imm5.ZeroExtend(); in thumb16_LDRB_imm()
209 const u32 imm32 = imm5.ZeroExtend() << 1; in thumb16_STRH_imm()
214 const u32 imm32 = imm5.ZeroExtend() << 1; in thumb16_LDRH_imm()
219 const u32 imm32 = imm8.ZeroExtend() << 2; in thumb16_STR_imm_t2()
224 const u32 imm32 = imm8.ZeroExtend() << 2; in thumb16_LDR_imm_t2()
229 const u32 imm32 = imm8.ZeroExtend() << 2; in thumb16_ADR()
[all …]
/dports/emulators/citra/citra-ac98458e0/externals/dynarmic/src/frontend/A32/disassembler/
H A Ddisassembler_thumb.cpp152 const u32 imm32 = imm8.ZeroExtend() << 2; in thumb16_LDR_literal()
189 const u32 imm32 = imm5.ZeroExtend() << 2; in thumb16_STR_imm_t1()
194 const u32 imm32 = imm5.ZeroExtend() << 2; in thumb16_LDR_imm_t1()
199 const u32 imm32 = imm5.ZeroExtend(); in thumb16_STRB_imm()
204 const u32 imm32 = imm5.ZeroExtend(); in thumb16_LDRB_imm()
209 const u32 imm32 = imm5.ZeroExtend() << 1; in thumb16_STRH_imm()
214 const u32 imm32 = imm5.ZeroExtend() << 1; in thumb16_LDRH_imm()
219 const u32 imm32 = imm8.ZeroExtend() << 2; in thumb16_STR_imm_t2()
224 const u32 imm32 = imm8.ZeroExtend() << 2; in thumb16_LDR_imm_t2()
229 const u32 imm32 = imm8.ZeroExtend() << 2; in thumb16_ADR()
[all …]
/dports/emulators/yuzu/yuzu-0b47f7a46/externals/dynarmic/src/frontend/A32/translate/impl/
H A Dmisc.cpp24 const u32 lsb_value = lsb.ZeroExtend(); in arm_BFC()
25 const u32 msb_value = msb.ZeroExtend(); in arm_BFC()
47 const u32 lsb_value = lsb.ZeroExtend(); in arm_BFI()
48 const u32 msb_value = msb.ZeroExtend(); in arm_BFI()
83 const IR::U32 imm16 = ir.Imm32(concatenate(imm4, imm12).ZeroExtend() << 16); in arm_MOVT()
100 const IR::U32 imm = ir.Imm32(concatenate(imm4, imm12).ZeroExtend()); in arm_MOVW()
112 const u32 lsb_value = lsb.ZeroExtend(); in arm_SBFX()
113 const u32 widthm1_value = widthm1.ZeroExtend(); in arm_SBFX()
159 const u32 lsb_value = lsb.ZeroExtend(); in arm_UBFX()
160 const u32 widthm1_value = widthm1.ZeroExtend(); in arm_UBFX()

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