Home
last modified time | relevance | path

Searched refs:arm_smmu_cb_write (Results 1 – 12 of 12) sorted by relevance

/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/iommu/arm/arm-smmu/
H A Darm-smmu.c264 arm_smmu_cb_write(smmu_domain->smmu, smmu_domain->cfg.cbndx, in arm_smmu_tlb_inv_context_s1()
295 arm_smmu_cb_write(smmu, idx, reg, iova); in arm_smmu_tlb_inv_range_s1()
323 arm_smmu_cb_write(smmu, idx, reg, iova); in arm_smmu_tlb_inv_range_s2()
424 arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_FSR, fsr); in arm_smmu_context_fault()
527 arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_SCTLR, 0); in arm_smmu_write_context_bank()
572 arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_TCR2, cb->tcr[1]); in arm_smmu_write_context_bank()
573 arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_TCR, cb->tcr[0]); in arm_smmu_write_context_bank()
578 arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_TTBR0, cb->ttbr[0]); in arm_smmu_write_context_bank()
579 arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_TTBR1, cb->ttbr[1]); in arm_smmu_write_context_bank()
604 arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_SCTLR, reg); in arm_smmu_write_context_bank()
[all …]
H A Darm-smmu-qcom.c32 arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_SCTLR, reg); in qcom_adreno_smmu_write_sctlr()
200 arm_smmu_cb_write(smmu, qsmmu->bypass_cbndx, ARM_SMMU_CB_SCTLR, 0); in qcom_smmu_cfg_probe()
H A Darm-smmu-impl.c138 arm_smmu_cb_write(smmu, i, ARM_SMMU_CB_ACTLR, reg); in arm_mmu500_reset()
H A Darm-smmu.h516 #define arm_smmu_cb_write(s, n, o, v) \ macro
/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/iommu/arm/arm-smmu/
H A Darm-smmu.c264 arm_smmu_cb_write(smmu_domain->smmu, smmu_domain->cfg.cbndx, in arm_smmu_tlb_inv_context_s1()
295 arm_smmu_cb_write(smmu, idx, reg, iova); in arm_smmu_tlb_inv_range_s1()
323 arm_smmu_cb_write(smmu, idx, reg, iova); in arm_smmu_tlb_inv_range_s2()
424 arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_FSR, fsr); in arm_smmu_context_fault()
527 arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_SCTLR, 0); in arm_smmu_write_context_bank()
572 arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_TCR2, cb->tcr[1]); in arm_smmu_write_context_bank()
573 arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_TCR, cb->tcr[0]); in arm_smmu_write_context_bank()
578 arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_TTBR0, cb->ttbr[0]); in arm_smmu_write_context_bank()
579 arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_TTBR1, cb->ttbr[1]); in arm_smmu_write_context_bank()
604 arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_SCTLR, reg); in arm_smmu_write_context_bank()
[all …]
H A Darm-smmu-qcom.c32 arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_SCTLR, reg); in qcom_adreno_smmu_write_sctlr()
200 arm_smmu_cb_write(smmu, qsmmu->bypass_cbndx, ARM_SMMU_CB_SCTLR, 0); in qcom_smmu_cfg_probe()
H A Darm-smmu-impl.c138 arm_smmu_cb_write(smmu, i, ARM_SMMU_CB_ACTLR, reg); in arm_mmu500_reset()
H A Darm-smmu.h516 #define arm_smmu_cb_write(s, n, o, v) \ macro
/dports/multimedia/libv4l/linux-5.13-rc2/drivers/iommu/arm/arm-smmu/
H A Darm-smmu.c264 arm_smmu_cb_write(smmu_domain->smmu, smmu_domain->cfg.cbndx, in arm_smmu_tlb_inv_context_s1()
295 arm_smmu_cb_write(smmu, idx, reg, iova); in arm_smmu_tlb_inv_range_s1()
323 arm_smmu_cb_write(smmu, idx, reg, iova); in arm_smmu_tlb_inv_range_s2()
424 arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_FSR, fsr); in arm_smmu_context_fault()
527 arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_SCTLR, 0); in arm_smmu_write_context_bank()
572 arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_TCR2, cb->tcr[1]); in arm_smmu_write_context_bank()
573 arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_TCR, cb->tcr[0]); in arm_smmu_write_context_bank()
578 arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_TTBR0, cb->ttbr[0]); in arm_smmu_write_context_bank()
579 arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_TTBR1, cb->ttbr[1]); in arm_smmu_write_context_bank()
604 arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_SCTLR, reg); in arm_smmu_write_context_bank()
[all …]
H A Darm-smmu-qcom.c32 arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_SCTLR, reg); in qcom_adreno_smmu_write_sctlr()
200 arm_smmu_cb_write(smmu, qsmmu->bypass_cbndx, ARM_SMMU_CB_SCTLR, 0); in qcom_smmu_cfg_probe()
H A Darm-smmu-impl.c138 arm_smmu_cb_write(smmu, i, ARM_SMMU_CB_ACTLR, reg); in arm_mmu500_reset()
H A Darm-smmu.h516 #define arm_smmu_cb_write(s, n, o, v) \ macro