bit\-vector\-= (reference) in projects: dports

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Searched +refs:bit +refs:vector (Results 1 – 25 of 36443) sorted by relevance

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/dports/lang/racket/racket-8.3/collects/data/
H A D	bit-vector.rkt	`32 (define bit-vector* 33 (let ([bit-vector 36 bit-vector)) 95 (bit-vector (bytes-copy (bit-vector-words bv)) 149 (define-vector-wraps "bit-vector" 151 bit-vector? bit-vector-length bit-vector-ref bit-vector-set! make-bit-vector 152 unsafe-bit-vector-ref bit-vector-set! bit-vector-length 154 in-bit-vector 227 [bit-vector? 229 [rename bit-vector* bit-vector [all …]`
/dports/lang/racket-minimal/racket-8.3/collects/data/
H A D	bit-vector.rkt	`32 (define bit-vector* 33 (let ([bit-vector 36 bit-vector)) 95 (bit-vector (bytes-copy (bit-vector-words bv)) 149 (define-vector-wraps "bit-vector" 151 bit-vector? bit-vector-length bit-vector-ref bit-vector-set! make-bit-vector 152 unsafe-bit-vector-ref bit-vector-set! bit-vector-length 154 in-bit-vector 227 [bit-vector? 229 [rename bit-vector* bit-vector [all …]`
/dports/lang/racket/racket-8.3/share/pkgs/data-doc/data/scribblings/
H A D	bit-vector.scrbl	`35 (bit-vector-ref (make-bit-vector 3) 2) 36 (bit-vector-ref (make-bit-vector 3 #t) 2) 46 (bit-vector-ref (bit-vector #f #t #f) 1) 55 @defproc[(bit-vector-ref [bv bit-vector?] 65 (bit-vector-ref (bit-vector #f #t) 1) 66 (bit-vector-ref (bit-vector #f #t) 5 'not-there) 87 @defproc[(bit-vector-length [bv bit-vector?]) 93 @defproc[(bit-vector-popcount [bv bit-vector?]) 99 (bit-vector-popcount (bit-vector #f #t #t))] 102 @defproc[(bit-vector-copy [bv bit-vector?] [all …]`
/dports/math/cvc4/CVC4-1.7/src/theory/bv/
H A D	kinds	19 "bit-vector type" 69 operator BITVECTOR_ASHR 2 "bit-vector arithmetic shift right (the two bit-vector parameters must ha… 70 operator BITVECTOR_LSHR 2 "bit-vector logical shift right (the two bit-vector parameters must have … 71 operator BITVECTOR_SHL 2 "bit-vector shift left (the two bit-vector parameters must have same width… 74 operator BITVECTOR_ULE 2 "bit-vector unsigned less than or equal (the two bit-vector parameters mus… 75 operator BITVECTOR_ULT 2 "bit-vector unsigned less than (the two bit-vector parameters must have sa… 77 operator BITVECTOR_UGT 2 "bit-vector unsigned greater than (the two bit-vector parameters must have… 78 operator BITVECTOR_SLE 2 "bit-vector signed less than or equal (the two bit-vector parameters must … 79 operator BITVECTOR_SLT 2 "bit-vector signed less than (the two bit-vector parameters must have same… 81 operator BITVECTOR_SGT 2 "bit-vector signed greater than (the two bit-vector parameters must have s… [all …]
/dports/devel/fbthrift/fbthrift-2021.12.27.00/thrift/compiler/test/fixtures/lazy_deserialization/gen-cpp2/
H A D	terse_writes_types.h	175 return {this->__fbthrift_field_field1, __isset.at(0), __isset.bit(0)}; in field1_ref() 185 return {this->__fbthrift_field_field1, __isset.at(0), __isset.bit(0)}; in field1_ref() 195 return {this->__fbthrift_field_field1, __isset.at(0), __isset.bit(0)}; in field1() 205 return {this->__fbthrift_field_field1, __isset.at(0), __isset.bit(0)}; in field1() 215 return {this->__fbthrift_field_field2, __isset.at(1), __isset.bit(1)}; in field2_ref() 225 return {this->__fbthrift_field_field2, __isset.at(1), __isset.bit(1)}; in field2_ref() 235 return {this->__fbthrift_field_field2, __isset.at(1), __isset.bit(1)}; in field2() 245 return {this->__fbthrift_field_field2, __isset.at(1), __isset.bit(1)}; in field2() 255 return {this->__fbthrift_field_field3, __isset.at(2), __isset.bit(2)}; in field3_ref() 265 return {this->__fbthrift_field_field3, __isset.at(2), __isset.bit(2)}; in field3_ref() [all …]
H A D	simple_types.h	233 …structor, ::std::vector<double> field1__arg, ::std::vector<::std::int32_t> field2__arg, ::std::vec… 260 return {this->__fbthrift_field_field1, __isset.at(0), __isset.bit(0)}; in field1_ref() 270 return {this->__fbthrift_field_field1, __isset.at(0), __isset.bit(0)}; in field1_ref() 280 return {this->__fbthrift_field_field1, __isset.at(0), __isset.bit(0)}; in field1() 290 return {this->__fbthrift_field_field1, __isset.at(0), __isset.bit(0)}; in field1() 300 return {this->__fbthrift_field_field2, __isset.at(1), __isset.bit(1)}; in field2_ref() 310 return {this->__fbthrift_field_field2, __isset.at(1), __isset.bit(1)}; in field2_ref() 320 return {this->__fbthrift_field_field2, __isset.at(1), __isset.bit(1)}; in field2() 330 return {this->__fbthrift_field_field2, __isset.at(1), __isset.bit(1)}; in field2() 340 return {this->__fbthrift_field_field3, __isset.at(2), __isset.bit(2)}; in field3_ref() [all …]
/dports/devel/fbthrift/fbthrift-2021.12.27.00/thrift/compiler/test/fixtures/templated-deserialize/gen-cpp2/
H A D	module_types.h	445 …::std::vector<::std::vector<::std::vector<::std::vector<::std::int32_t>>>> __fbthrift_field_fieldK; 876 …template <typename..., typename T = ::std::vector<::std::vector<::std::vector<::std::vector<::std:… 881 …template <typename..., typename T = ::std::vector<::std::vector<::std::vector<::std::vector<::std:… 886 …template <typename..., typename T = ::std::vector<::std::vector<::std::vector<::std::vector<::std:… 891 …template <typename..., typename T = ::std::vector<::std::vector<::std::vector<::std::vector<::std:… 896 …template <typename..., typename T = ::std::vector<::std::vector<::std::vector<::std::vector<::std:… 901 …template <typename..., typename T = ::std::vector<::std::vector<::std::vector<::std::vector<::std:… 906 …template <typename..., typename T = ::std::vector<::std::vector<::std::vector<::std::vector<::std:… 911 …template <typename..., typename T = ::std::vector<::std::vector<::std::vector<::std::vector<::std:… 1314 …const ::std::vector<::std::vector<::std::vector<::std::vector<::std::int32_t>>>>& get_fieldK() con… [all …]
/dports/devel/libsimdpp/libsimdpp-2.1-400-g9dac213d/doc/wiki/shuffle/
H A D	permute_bytes16.mwiki	12 Each byte within the {{tt\|mask}} defines which element to select for the output vector: 14 * Bits 3-0 define the element within the selected vector. 22 {{vset4 u \| ''promoted 8-bit vector'' \| ''any 8-bit vector'' \| ''any 8-bit vector'' \| {{tt\|uint8}} … 23 {{vset4 u \| ''promoted 16-bit vector'' \| ''any 16-bit vector'' \| ''any 16-bit vector'' \| {{tt\|uint1… 24 {{vset4 u \| ''promoted 32-bit vector'' \| ''any 32-bit vector'' \| ''any 32-bit vector'' \| {{tt\|uint3… 25 {{vset4 u \| ''promoted 64-bit vector'' \| ''any 64-bit vector'' \| ''any 64-bit vector'' \| {{tt\|uint6… 28 …type of the return vector is governed by the [[types/promotion\|expression promotion]] rules. The r… 30 …bit lanes. The {{tt\|n}}-th lane in the return vector is governed by {{tt\|n}}-th lane of the {{tt\|m… 34 {{par \| a \| source vector }} 35 {{par \| mask \| mask vector}} [all …]
H A D	permute_zbytes16.mwiki	12 Each byte within the {{tt\|mask}} defines which element to select for the output vector: 15 * Bits 3-0 define the element within the selected vector. 23 {{vset4 u \| ''promoted 8-bit vector'' \| ''any 8-bit vector'' \| ''any 8-bit vector'' \| {{tt\|uint8}} … 24 {{vset4 u \| ''promoted 16-bit vector'' \| ''any 16-bit vector'' \| ''any 16-bit vector'' \| {{tt\|uint1… 25 {{vset4 u \| ''promoted 32-bit vector'' \| ''any 32-bit vector'' \| ''any 32-bit vector'' \| {{tt\|uint3… 26 {{vset4 u \| ''promoted 64-bit vector'' \| ''any 64-bit vector'' \| ''any 64-bit vector'' \| {{tt\|uint6… 29 …type of the return vector is governed by the [[types/promotion\|expression promotion]] rules. The r… 31 …bit lanes. The {{tt\|n}}-th lane in the return vector is governed by {{tt\|n}}-th lane of the {{tt\|m… 35 {{par \| a \| source vector }} 36 {{par \| mask \| mask vector}} [all …]
H A D	shuffle_bytes16.mwiki	13 Each byte within the {{tt\|mask}} defines which element to select for the output vector: 15 * Bit 4 defines which vector to select. {{c\|0}} corresponds to {{tt\|a}}, {{c\|1}} to {{tt\|b}}. 16 * Bits 3-0 define the element within the selected vector. 24 {{vset4 u \| ''promoted 8-bit vector'' \| ''any 8-bit vector'' \| ''any 8-bit vector'' \| {{tt\|uint8}} … 25 {{vset4 u \| ''promoted 16-bit vector'' \| ''any 16-bit vector'' \| ''any 16-bit vector'' \| {{tt\|uint1… 26 {{vset4 u \| ''promoted 32-bit vector'' \| ''any 32-bit vector'' \| ''any 32-bit vector'' \| {{tt\|uint3… 27 {{vset4 u \| ''promoted 64-bit vector'' \| ''any 64-bit vector'' \| ''any 64-bit vector'' \| {{tt\|uint6… 30 …type of the return vector is governed by the [[types/promotion\|expression promotion]] rules. The r… 32 …bit lanes. The {{tt\|n}}-th lane in the return vector is governed by {{tt\|n}}-th lane of the {{tt\|m… 37 {{par \| mask \| mask vector}} [all …]
H A D	shuffle_zbytes16.mwiki	13 Each byte within the {{tt\|mask}} defines which element to select for the output vector: 16 * Bit 4 defines which vector to select. {{c\|0}} corresponds to {{tt\|a}}, {{c\|1}} to {{tt\|b}}. 17 * Bits 3-0 define the element within the selected vector. 25 {{vset4 u \| ''promoted 8-bit vector'' \| ''any 8-bit vector'' \| ''any 8-bit vector'' \| {{tt\|uint8}} … 26 {{vset4 u \| ''promoted 16-bit vector'' \| ''any 16-bit vector'' \| ''any 16-bit vector'' \| {{tt\|uint1… 27 {{vset4 u \| ''promoted 32-bit vector'' \| ''any 32-bit vector'' \| ''any 32-bit vector'' \| {{tt\|uint3… 28 {{vset4 u \| ''promoted 64-bit vector'' \| ''any 64-bit vector'' \| ''any 64-bit vector'' \| {{tt\|uint6… 31 …type of the return vector is governed by the [[types/promotion\|expression promotion]] rules. The r… 33 …bit lanes. The {{tt\|n}}-th lane in the return vector is governed by {{tt\|n}}-th lane of the {{tt\|m… 38 {{par \| mask \| mask vector}} [all …]
/dports/math/p5-Bit-Vector/Bit-Vector-7.4/
H A D	Vector.pod	`790 If both bit vector arguments have length zero, the resulting bit vector 867 Copies the contents of bit vector "C<$vec1>" to bit vector "C<$vec2>". 1143 bit vector. 1322 representing one bit vector into another bit vector of different 1380 representing one bit vector into another bit vector of different 2126 bit vector "C<$vec1>", the contents of bit vector "C<$vec1>" are copied 2419 bit vector. 2434 bit vector. 2658 bit vector: 2679 bit vector: [all …]`
/dports/net-p2p/qtum/qtum-mainnet-fastlane-v0.20.3/src/util/
H A D	asmap.cpp	11 …DecodeBits(std::vector<bool>::const_iterator& bitpos, const std::vector<bool>::const_iterator& end… in DecodeBits() 14 bool bit; in DecodeBits() local 19 bit = bitpos; in DecodeBits() 22 bit = 0; in DecodeBits() 24 if (bit) { in DecodeBits() 29 bit = bitpos; in DecodeBits() 31 val += bit << (*bit_sizes_it - 1 - b); in DecodeBits() 46 uint32_t DecodeASN(std::vector<bool>::const_iterator& bitpos, const std::vector<bool>::const_iterat… in DecodeASN() 67 uint32_t Interpret(const std::vector<bool> &asmap, const std::vector<bool> &ip) in Interpret() 89 for (uint32_t bit = 0; bit < matchlen; bit++) { in Interpret() local [all …]
/dports/graphics/vapoursynth-waifu2x-ncnn-vulkan/vapoursynth-waifu2x-ncnn-vulkan-r4/deps/ncnn/docs/developer-guide/
H A D	arm-a53-a55-dual-issue.md	12 * 128bit vector load cannot be dual issued with fmla, wait 2 cycles 13 * 64bit vector load cannot be dual issued with fmla, wait 1 cycle 16 * 64bit vector load and 64bit vector insert can be dual issued, no penalty 20 * use 64bit vector load only 21 * issue vector load every three fmla 25 * insert 64bit into vector from integer register, dual issue with the next interleaved 64bit load 54 * 128bit vector load cannot be dual issued with fmla, wait 2 cycles 55 * 64bit vector load can be dual issued with fmla, no penalty 58 * 64bit vector insert can be dual issued with fmla, no penalty 61 * use 64bit vector load only [all …]
/dports/graphics/waifu2x-ncnn-vulkan/waifu2x-ncnn-vulkan-20210521/src/ncnn/docs/developer-guide/
H A D	arm-a53-a55-dual-issue.md	12 * 128bit vector load cannot be dual issued with fmla, wait 2 cycles 13 * 64bit vector load cannot be dual issued with fmla, wait 1 cycle 16 * 64bit vector load and 64bit vector insert can be dual issued, no penalty 20 * use 64bit vector load only 21 * issue vector load every three fmla 25 * insert 64bit into vector from integer register, dual issue with the next interleaved 64bit load 54 * 128bit vector load cannot be dual issued with fmla, wait 2 cycles 55 * 64bit vector load can be dual issued with fmla, no penalty 58 * 64bit vector insert can be dual issued with fmla, no penalty 61 * use 64bit vector load only [all …]
/dports/benchmarks/vkpeak/vkpeak-20210430/ncnn/docs/developer-guide/
H A D	arm-a53-a55-dual-issue.md	12 * 128bit vector load cannot be dual issued with fmla, wait 2 cycles 13 * 64bit vector load cannot be dual issued with fmla, wait 1 cycle 16 * 64bit vector load and 64bit vector insert can be dual issued, no penalty 20 * use 64bit vector load only 21 * issue vector load every three fmla 25 * insert 64bit into vector from integer register, dual issue with the next interleaved 64bit load 54 * 128bit vector load cannot be dual issued with fmla, wait 2 cycles 55 * 64bit vector load can be dual issued with fmla, no penalty 58 * 64bit vector insert can be dual issued with fmla, no penalty 61 * use 64bit vector load only [all …]
/dports/misc/ncnn/ncnn-20211208/docs/developer-guide/
H A D	arm-a53-a55-dual-issue.md	12 * 128bit vector load cannot be dual issued with fmla, wait 2 cycles 13 * 64bit vector load cannot be dual issued with fmla, wait 1 cycle 16 * 64bit vector load and 64bit vector insert can be dual issued, no penalty 20 * use 64bit vector load only 21 * issue vector load every three fmla 25 * insert 64bit into vector from integer register, dual issue with the next interleaved 64bit load 54 * 128bit vector load cannot be dual issued with fmla, wait 2 cycles 55 * 64bit vector load can be dual issued with fmla, no penalty 58 * 64bit vector insert can be dual issued with fmla, no penalty 61 * use 64bit vector load only [all …]
/dports/graphics/realsr-ncnn-vulkan/realsr-ncnn-vulkan-20210210/src/ncnn/docs/developer-guide/
H A D	arm-a53-a55-dual-issue.md	12 * 128bit vector load cannot be dual issued with fmla, wait 2 cycles 13 * 64bit vector load cannot be dual issued with fmla, wait 1 cycle 16 * 64bit vector load and 64bit vector insert can be dual issued, no penalty 20 * use 64bit vector load only 21 * issue vector load every three fmla 25 * insert 64bit into vector from integer register, dual issue with the next interleaved 64bit load 54 * 128bit vector load cannot be dual issued with fmla, wait 2 cycles 55 * 64bit vector load can be dual issued with fmla, no penalty 58 * 64bit vector insert can be dual issued with fmla, no penalty 61 * use 64bit vector load only [all …]
/dports/devel/libsimdpp/libsimdpp-2.1-400-g9dac213d/doc/wiki/
H A D	types.mwiki	15 {{dsc tclass \| types/uint8_void \| title=uint8{{small\|<N,void>}} \| vector containing unsigned 8-bit … 16 {{dsc tclass \| types/int8_void \| title=int8{{small\|<N,void>}} \| vector containing signed 8-bit inte… 18 …lass \| types/uint16_void \| title=uint16{{small\|<N,void>}} \| vector containing unsigned 16-bit inte… 19 {{dsc tclass \| types/int16_void \| title=int16{{small\|<N,void>}} \| vector containing signed 16-bit i… 22 {{dsc tclass \| types/int32_void \| title=int32{{small\|<N,void>}} \| vector containing signed 32-bit i… 25 {{dsc tclass \| types/int64_void \| title=int64{{small\|<N,void>}} \| vector containing signed 64-bit i… 41 {{dsc tclass \| types/uint8_expr \| title=uint8{{small\|<N,E>}} \| vector containing unsigned 8-bit int… 42 {{dsc tclass \| types/int8_expr \| title=int8{{small\|<N,E>}} \| vector containing signed 8-bit integer… 45 {{dsc tclass \| types/int16_expr \| title=int16{{small\|<N,E>}} \| vector containing signed 16-bit inte… 48 {{dsc tclass \| types/int32_expr \| title=int32{{small\|<N,E>}} \| vector containing signed 32-bit inte… [all …]
/dports/math/p5-Bit-Vector/Bit-Vector-7.4/lib/Bit/Vector/
H A D	Overload.pod	`450 I.e., bit #0 of any given bit vector corresponds to bit #0 of word #0 in the 631 "C<$vector ^= 5;>" will flip bit #5 in the given bit vector (this is 795 bit vector are cleared. 818 of the given bit vector. 827 of the given bit vector. 844 stored in the given bit vector. 864 bit vector object! 1006 exponentiation of the left bit vector elevated to the right bit vector's 1114 two bit vector operands. 1169 given bit vector. [all …]`
/dports/lang/sdcc/sdcc-4.0.0/device/include/mcs51/
H A D	compiler.h	79 # define SBIT(name, addr, bit) __sbit __at(addr+bit) name argument 88 # define INTERRUPT(name, vector) void name (void) __interrupt (vector) argument 98 # define SBIT(name, addr, bit) sbit name = addr^bit argument 107 # define INTERRUPT(name, vector) void name (void) interrupt vector argument 118 # define SBIT(name, addr, bit) at (addr+bit) sbit name argument 127 # define INTERRUPT(name, vector) void name (void) interrupt vector argument 137 # define SBIT(name, addr, bit) __bit __no_init volatile bool name @ (addr+bit) argument 159 # define SBIT(name, addr, bit) _sfrbit name _at(addr+bit) argument 183 # define SBIT(name, addr, bit) volatile bit name @ (addr+bit) argument 202 # define SBIT(name, addr, bit) _sfrbit name = (addr+bit) argument [all …]
/dports/devel/fbthrift/fbthrift-2021.12.27.00/thrift/compiler/test/fixtures/complex-struct/gen-cpp2/
H A D	module_types.h	2983 …template <typename..., typename T = ::std::vector<::std::vector<::std::vector<::std::vector<::cpp2… 2988 …template <typename..., typename T = ::std::vector<::std::vector<::std::vector<::std::vector<::cpp2… 2993 …template <typename..., typename T = ::std::vector<::std::vector<::std::vector<::std::vector<::cpp2… 2998 …template <typename..., typename T = ::std::vector<::std::vector<::std::vector<::std::vector<::cpp2… 3003 …template <typename..., typename T = ::std::vector<::std::vector<::std::vector<::std::vector<::cpp2… 3008 …template <typename..., typename T = ::std::vector<::std::vector<::std::vector<::std::vector<::cpp2… 3013 …template <typename..., typename T = ::std::vector<::std::vector<::std::vector<::std::vector<::cpp2… 3018 …template <typename..., typename T = ::std::vector<::std::vector<::std::vector<::std::vector<::cpp2… 3672 …::std::vector<::std::vector<::std::vector<::std::vector<::cpp2::MyEnum>>>> get_listofListOfListOfL… 6354 ::std::vector<::std::vector<float>>& set_setFloat(::std::vector<::std::vector<float>> const &t) { [all …]
/dports/security/clamav-lts/clamav-0.103.5/libclamav/c++/llvm/include/llvm/CodeGen/
H A D	ValueTypes.td	23 def i1 : ValueType<1 , 1>; // One bit boolean value 24 def i8 : ValueType<8 , 2>; // 8-bit integer value 25 def i16 : ValueType<16 , 3>; // 16-bit integer value 26 def i32 : ValueType<32 , 4>; // 32-bit integer value 27 def i64 : ValueType<64 , 5>; // 64-bit integer value 28 def i128 : ValueType<128, 6>; // 128-bit integer value 29 def f32 : ValueType<32 , 7>; // 32-bit floating point value 30 def f64 : ValueType<64 , 8>; // 64-bit floating point value 31 def f80 : ValueType<80 , 9>; // 80-bit floating point value 32 def f128 : ValueType<128, 10>; // 128-bit floating point value [all …]
/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/shell-encryption/src/
H A D	transcription_test.cc	128 std::vector<InputInt> input(len, 0); in TYPED_TEST() 148 std::vector<InputInt> bits_i(kLength, 0); in TYPED_TEST() 193 std::vector<OutputInt> bits_j, in TYPED_TEST() 200 for (int bit = 0; bit < i * len; bit++) { in TYPED_TEST() local 236 std::vector<OutputInt> bits_j, in TYPED_TEST() 241 std::vector<InputInt> bits_i2, in TYPED_TEST() 328 for (int bit = 0; bit < i * len; bit++) { in TYPED_TEST() local 373 for (int bit = 0; bit < i * len; bit++) { in TYPED_TEST() local 416 for (int bit = 0; bit < i * len; bit++) { in TYPED_TEST() local 444 std::vector<InputInt> bits_i( in TYPED_TEST() [all …]
/dports/cad/yosys/yosys-yosys-0.12/passes/sat/
H A D	freduce.cc	54 return bit < other.bit; in operator <() 196 std::vector<int> model_expr; in analyze() 197 std::vector<bool> model; in analyze() 241 std::vector<int> out_depth; 306 void analyze_const(std::vector<std::vector<equiv_bit_t>> &results, int idx) in analyze_const() 338 bit.bit = value; in analyze_const() 375 std::vector<bool> model; in analyze() 491 void analyze(std::vector<std::vector<equiv_bit_t>> &results, int perc) in analyze() 493 std::vector<int> bucket; in analyze() 645 std::map<std::vector<RTLIL::SigBit>, std::vector<RTLIL::SigBit>> buckets; in run() [all …]

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