1 /* 2 * Simulator of microcontrollers (regs51.h) 3 * 4 * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. 5 * 6 * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu 7 * 8 */ 9 10 /* This file is part of microcontroller simulator: ucsim. 11 12 UCSIM is free software; you can redistribute it and/or modify 13 it under the terms of the GNU General Public License as published by 14 the Free Software Foundation; either version 2 of the License, or 15 (at your option) any later version. 16 17 UCSIM is distributed in the hope that it will be useful, 18 but WITHOUT ANY WARRANTY; without even the implied warranty of 19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 GNU General Public License for more details. 21 22 You should have received a copy of the GNU General Public License 23 along with UCSIM; see the file COPYING. If not, write to the Free 24 Software Foundation, 59 Temple Place - Suite 330, Boston, MA 25 02111-1307, USA. */ 26 /*@1@*/ 27 28 #ifndef REGS51_HEADER 29 #define REGS51_HEADER 30 31 32 /* Address of SFR registers */ 33 34 #define ACC 0xe0 /* Accumulator */ 35 #define B 0xf0 /* B register (scondary accumulator) */ 36 #define PSW 0xd0 /* Program Status Word */ 37 #define SP 0x81 /* Stack Pointer */ 38 #define DPL 0x82 /* Data Pointer Low byte */ 39 #define DPH 0x83 /* Data Pointer High byte */ 40 #define DPL1 0x84 /* 2nd Data Pointer Low byte */ 41 #define DPH1 0x85 /* 2nd Data Pointer High byte */ 42 #define DPS 0x86 /* DPS 1H=DPTR is DPL1/DPH1, 2H=AUTO DPTR INCR */ 43 #define P0 0x80 /* Port #0 */ 44 #define P1 0x90 /* Port #1 */ 45 #define P2 0xa0 /* Port #2 */ 46 #define P3 0xb0 /* Port #3 */ 47 #define IP 0xb8 /* Intrrupt Priority */ 48 #define IE 0xa8 /* Interrupt Enable */ 49 #define TMOD 0x89 /* Timer MODe */ 50 #define TCON 0x88 /* Timer CONtrol */ 51 #define T2CON 0xc8 /* Timer #2 CONtrol */ 52 #define TH0 0x8c /* Timer #0 High byte */ 53 #define TL0 0x8a /* Timer #0 Low byte */ 54 #define TH1 0x8d /* Timer #1 High byte */ 55 #define TL1 0x8b /* Timer #1 Low byte */ 56 #define SCON 0x98 /* Serial line CONtrol */ 57 #define TH2 0xcd /* Timer #2 High byte */ 58 #define TL2 0xcc /* Timer #2 Low byte */ 59 #define RCAP2H 0xcb /* Capture Register of Timer #2 High byte */ 60 #define RCAP2L 0xca /* Capture Register of Timer #2 Low byte */ 61 #define SBUF 0x99 /* Serial line BUFfer */ 62 #define PCON 0x87 /* Power CONtrol */ 63 64 #define AUXR 0x8e /* Auxiliary Register */ 65 #define AUXR1 0xa2 /* Secondary Aux Register */ 66 67 #define P4 0x80 68 #define DPXL 0x84 /* */ 69 //#define DPL1 0x84 /* 2nd Data Pointer Low byte */ 70 //#define DPH1 0x85 /* 2nd Data Pointer High byte */ 71 #define DPS 0x86 /* DPS 1H=DPTR is DPL1/DPH1,... */ 72 #define CKCON 0x8E /* Clock Control */ 73 #define EXIF 0x91 /* */ 74 #define P4CNT 0x92 /* */ 75 #define DPX 0x93 /* Data Pointer HHigh byte */ 76 #define DPX1 0x95 /* Data Pointer HHigh byte */ 77 #define R51_ESP 0x9b /* Extended Stack Pointer */ 78 #define AP 0x9c /* Address Page */ 79 #define ACON 0x9d /* */ 80 #define P5 0xa1 81 #define P5CNT 0xa2 /* */ 82 #define C0C 0xa3 /* */ 83 #define WDTRST 0xa6 /* */ 84 #define IE0 0xa8 /* */ 85 #define SADDR 0xa9 /* */ 86 #define IPH0 0xb7 /* */ 87 #define IPH 0xb7 88 #define IPL0 0xb8 /* */ 89 #define SADEN 0xb9 /* */ 90 #define SPH 0xbd /* */ 91 #define PMR 0xc4 /* */ 92 #define MCON 0xc6 /* */ 93 #define TA 0xc7 /* */ 94 #define T2MOD 0xc9 /* */ 95 #define COR 0xce /* */ 96 #define PSW1 0xd1 /* */ 97 #define MCNT0 0xd1 98 #define MCNT1 0xd2 99 #define MA 0xd3 /* MA register from math accelerator */ 100 #define MB 0xd4 /* MB register from math accelerator */ 101 #define MC 0xd5 /* MC register from math accelerator */ 102 #define CCON 0xd8 /* */ 103 #define CMOD 0xd9 /* */ 104 #define WDCON 0xd8 /* */ 105 #define CCAPM0 0xda /* */ 106 #define CCAPM1 0xdb /* */ 107 #define CCAPM2 0xdc /* */ 108 #define CCAPM3 0xdd /* */ 109 #define CCAPM4 0xde /* */ 110 #define C1C 0xe3 /* */ 111 #define CL 0xe9 /* */ 112 #define CCAP0L 0xea /* */ 113 #define CCAP1L 0xeb /* */ 114 #define CCAP2L 0xec /* */ 115 #define CCAP3L 0xed /* */ 116 #define CCAP4L 0xee /* */ 117 #define CH 0xf9 /* */ 118 #define CCAP0H 0xfa /* */ 119 #define CCAP1H 0xfb /* */ 120 #define CCAP2H 0xfc /* */ 121 #define CCAP3H 0xfd /* */ 122 #define CCAP4H 0xfe /* */ 123 124 /* Bit masks of flag bits in PSW (0xd0)*/ 125 126 #define bmCY 0x80 /* carry */ 127 #define bmAC 0x40 /* acarry */ 128 #define bmF0 0x20 /* flag 0 */ 129 #define bmRS1 0x10 /* register select 1 */ 130 #define bmRS0 0x08 /* register select 0 */ 131 #define bmOV 0x04 /* arithmetic overflow */ 132 #define bmP 0x01 /* parity, set by hardware */ 133 134 /* Bit masks in PCON (0x87) */ 135 136 #define bmSMOD1 0x80 137 #define bmSMOD 0x80 138 #define bmSMOD0 0x40 139 #define bmPOF 0x10 140 #define bmGF1 0x08 141 #define bmGF0 0x04 142 #define bmPD 0x02 143 #define bmIDL 0x01 144 145 /* Bit masks in IE (0xa8) */ 146 147 #define bmEA 0x80 148 #define bmEC 0x40 149 #define bmET2 0x20 150 #define bmES 0x10 151 #define bmET1 0x08 152 #define bmEX1 0x04 153 #define bmET0 0x02 154 #define bmEX0 0x01 155 156 /* Bit masks in IP (0xb8) */ 157 158 #define bmPPC 0x40 159 #define bmPT2 0x20 160 #define bmPS 0x10 161 #define bmPT1 0x08 162 #define bmPX1 0x04 163 #define bmPT0 0x02 164 #define bmPX0 0x01 165 166 /* Bit masks in IPL0 (0xb8) */ 167 168 #define bmIPL0_6 0x40 169 #define bmIPL0_5 0x20 170 #define bmIPL0_4 0x10 171 #define bmIPL0_3 0x08 172 #define bmIPL0_2 0x04 173 #define bmIPL0_1 0x02 174 #define bmIPL0_0 0x01 175 176 /* Bit masks in IPH0 (0xb7) */ 177 178 #define bmIPH0_6 0x40 179 #define bmIPH0_5 0x20 180 #define bmIPH0_4 0x10 181 #define bmIPH0_3 0x08 182 #define bmIPH0_2 0x04 183 #define bmIPH0_1 0x02 184 #define bmIPH0_0 0x01 185 186 /* Bit masks in P1 (0x90) */ 187 188 #define bmCEX4 0x80 189 #define bmCEX3 0x40 190 #define bmCEX2 0x20 191 #define bmCEX1 0x10 192 #define bmCEX0 0x08 193 #define bmECI 0x04 194 #define bmT2EX 0x02 195 #define bmT2 0x01 196 197 /* Bit masks in P3 (0xb0) */ 198 199 #define bmRXD 0x01 200 #define bmTXD 0x02 201 #define bm_INT0 0x04 202 #define bm_INT1 0x08 203 #define bmT0 0x10 204 #define bmT1 0x20 205 #define bm_WR 0x40 206 #define bm_RD 0x80 207 208 /* Bit masks in TMOD (0x89) */ 209 210 #define bmGATE1 0x80 211 #define bmC_T1 0x40 212 #define bmM11 0x20 213 #define bmM01 0x10 214 #define bmGATE0 0x08 215 #define bmC_T0 0x04 216 #define bmM10 0x02 217 #define bmM00 0x01 218 219 /* Bit masks in TCON (0x88) */ 220 221 #define bmTF1 0x80 222 #define bmTR1 0x40 223 #define bmTF0 0x20 224 #define bmTR0 0x10 225 #define bmIE1 0x08 226 #define bmIT1 0x04 227 #define bmIE0 0x02 228 #define bmIT0 0x01 229 230 /* Bit masks in AUXR (0x8e) */ 231 232 #define bmEXTRAM 0x02 233 #define bmDISABLE 0x01 234 235 /* Bit masks in AUXR1 (0xa2) */ 236 237 #define bmENBOOT 0x20 238 #define bmGF2 0x08 239 #define bmDPS 0x01 240 241 /* Bit masks in T2CON (0xc8) */ 242 243 #define bmTF2 0x80 244 #define bmEXF2 0x40 245 #define bmRCLK 0x20 246 #define bmTCLK 0x10 247 #define bmEXEN2 0x08 248 #define bmTR2 0x04 249 #define bmC_T2 0x02 250 #define bmCP_RL2 0x01 251 252 /* Bit masks in SCON (0x98) */ 253 254 #define bmFE_SM0 0x80 255 #define bmFE 0x80 256 #define bmSM0 0x80 257 #define bmSM1 0x40 258 #define bmSM2 0x20 259 #define bmREN 0x10 260 #define bmTB8 0x08 261 #define bmRB8 0x04 262 #define bmTI 0x02 263 #define bmRI 0x01 264 265 /* Bit masks in T2MOD (0xc9) */ 266 267 #define bmT2OE 0x02 268 #define bmDCEN 0x01 269 270 /* Bit masks in CMOD (0xd9) */ 271 272 #define bmCIDL 0x80 273 #define bmWDTE 0x40 274 #define bmCPS1 0x04 275 #define bmCPS0 0x02 276 #define bmECF 0x01 277 278 /* Bit masks in CCON (0xd8) */ 279 280 #define bmCF 0x80 281 #define bmCR 0x40 282 #define bmCCF4 0x10 283 #define bmCCF3 0x08 284 #define bmCCF2 0x04 285 #define bmCCF1 0x02 286 #define bmCCF0 0x01 287 288 /* Bit masks in CCAPM0 (0xda) */ 289 290 #define bmECOM0 0x40 291 #define bmCAPP0 0x20 292 #define bmCAPN0 0x10 293 #define bmMAT0 0x08 294 #define bmTOG0 0x04 295 #define bmPWM0 0x02 296 #define bmECCF0 0x01 297 298 /* Bit masks in CCAPM1 (0xdb) */ 299 300 #define bmECOM1 0x40 301 #define bmCAPP1 0x20 302 #define bmCAPN1 0x10 303 #define bmMAT1 0x08 304 #define bmTOG1 0x04 305 #define bmPWM1 0x02 306 #define bmECCF1 0x01 307 308 /* Bit masks in CCAPM2 (0xdc) */ 309 310 #define bmECOM2 0x40 311 #define bmCAPP2 0x20 312 #define bmCAPN2 0x10 313 #define bmMAT2 0x08 314 #define bmTOG2 0x04 315 #define bmPWM2 0x02 316 #define bmECCF2 0x01 317 318 /* Bit masks in CCAPM3 (0xdd) */ 319 320 #define bmECOM3 0x40 321 #define bmCAPP3 0x20 322 #define bmCAPN3 0x10 323 #define bmMAT3 0x08 324 #define bmTOG3 0x04 325 #define bmPWM3 0x02 326 #define bmECCF3 0x01 327 328 /* Bit masks in CCAPM4 (0xde) */ 329 330 #define bmECOM4 0x40 331 #define bmCAPP4 0x20 332 #define bmCAPN4 0x10 333 #define bmMAT4 0x08 334 #define bmTOG4 0x04 335 #define bmPWM4 0x02 336 #define bmECCF4 0x01 337 338 #define bmECOM 0x40 339 #define bmCAPP 0x20 340 #define bmCAPN 0x10 341 #define bmMAT 0x08 342 #define bmTOG 0x04 343 #define bmPWM 0x02 344 #define bmEDDF 0x01 345 346 347 #endif 348 349 /* End of s51.src/regs51.h */ 350