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Searched refs:c_addi4spn (Results 1 – 23 of 23) sorted by relevance

/dports/emulators/qemu-utils/qemu-4.2.1/target/riscv/
H A Dinsn16.decode74 @c_addi4spn ... . ..... ..... .. &i imm=%nzuimm_ciw rs1=2 rd=%rs2_3
88 addi 000 ... ... .. ... 00 @c_addi4spn
/dports/emulators/qemu5/qemu-5.2.0/target/riscv/
H A Dinsn16.decode74 @c_addi4spn ... . ..... ..... .. &i imm=%nzuimm_ciw rs1=2 rd=%rs2_3
88 addi 000 ... ... .. ... 00 @c_addi4spn
/dports/emulators/qemu-guest-agent/qemu-5.0.1/target/riscv/
H A Dinsn16.decode74 @c_addi4spn ... . ..... ..... .. &i imm=%nzuimm_ciw rs1=2 rd=%rs2_3
88 addi 000 ... ... .. ... 00 @c_addi4spn
/dports/emulators/qemu42/qemu-4.2.1/target/riscv/
H A Dinsn16.decode74 @c_addi4spn ... . ..... ..... .. &i imm=%nzuimm_ciw rs1=2 rd=%rs2_3
88 addi 000 ... ... .. ... 00 @c_addi4spn
/dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/target/riscv/
H A Dinsn16.decode74 @c_addi4spn ... . ..... ..... .. &i imm=%nzuimm_ciw rs1=2 rd=%rs2_3
88 addi 000 ... ... .. ... 00 @c_addi4spn
/dports/emulators/qemu60/qemu-6.0.0/target/riscv/
H A Dinsn16.decode74 @c_addi4spn ... . ..... ..... .. &i imm=%nzuimm_ciw rs1=2 rd=%rs2_3
88 addi 000 ... ... .. ... 00 @c_addi4spn
/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/target/riscv/
H A Dinsn16.decode74 @c_addi4spn ... . ..... ..... .. &i imm=%nzuimm_ciw rs1=2 rd=%rs2_3
88 addi 000 ... ... .. ... 00 @c_addi4spn
/dports/emulators/qemu/qemu-6.2.0/target/riscv/
H A Dinsn16.decode74 @c_addi4spn ... . ..... ..... .. &i imm=%nzuimm_ciw rs1=2 rd=%rs2_3
88 addi 000 ... ... .. ... 00 @c_addi4spn
/dports/lang/v8/v8-9.6.180.12/test/cctest/
H A Dtest-disasm-riscv64.cc475 COMPARE(c_addi4spn(a1, 924), "00000f6c addi a1, sp, 924"); in TEST()
H A Dtest-assembler-riscv64.cc1275 __ c_addi4spn(a0, 924); in TEST() local
/dports/emulators/riscv-isa-sim/riscv-isa-sim-4f12984/riscv/
H A Driscv.mk.in149 c_addi4spn \
H A Dencoding.h3505 DECLARE_INSN(c_addi4spn, MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN)
/dports/devel/radare2/radare2-5.1.1/libr/asm/arch/riscv/
H A Driscv-opc.h989 DECLARE_INSN(c_addi4spn, MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN)
/dports/lang/sdcc/sdcc-4.0.0/support/sdbinutils/include/opcode/
H A Driscv-opc.h1043 DECLARE_INSN(c_addi4spn, MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN)
/dports/devel/binutils/binutils-2.37/include/opcode/
H A Driscv-opc.h1123 DECLARE_INSN(c_addi4spn, MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN)
/dports/devel/arm-elf-binutils/binutils-2.37/include/opcode/
H A Driscv-opc.h1123 DECLARE_INSN(c_addi4spn, MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN)
/dports/devel/gnulibiberty/binutils-2.37/include/opcode/
H A Driscv-opc.h1123 DECLARE_INSN(c_addi4spn, MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN)
/dports/devel/gdb/gdb-11.1/include/opcode/
H A Driscv-opc.h1123 DECLARE_INSN(c_addi4spn, MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN)
/dports/emulators/riscv-isa-sim/riscv-isa-sim-4f12984/disasm/
H A Ddisasm.cc1048 DISASM_INSN("c.addi4spn", c_addi4spn, 0, {&rvc_rs2s, &rvc_sp, &rvc_addi4spn_imm}); in disassembler_t()
/dports/lang/v8/v8-9.6.180.12/src/codegen/riscv64/
H A Dassembler-riscv64.h628 void c_addi4spn(Register rd, int16_t uimm10);
H A Dassembler-riscv64.cc2220 void Assembler::c_addi4spn(Register rd, int16_t uimm10) { in c_addi4spn() function in v8::internal::Assembler
H A Dmacro-assembler-riscv64.cc430 c_addi4spn(rd, static_cast<uint16_t>(rt.immediate())); in Add64()
/dports/devel/openocd/openocd-0.11.0/src/target/riscv/
H A Dencoding.h2301 DECLARE_INSN(c_addi4spn, MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN)