| /dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/target/riscv/ |
| H A D | insn16.decode | 66 @c_lwsp ... . ..... ..... .. &i imm=%uimm_6bit_lw rs1=2 %rd
138 lw 010 . ..... ..... 10 @c_lwsp
157 flw 011 . ..... ..... 10 @c_lwsp
|
| /dports/emulators/qemu/qemu-6.2.0/target/riscv/ |
| H A D | insn16.decode | 66 @c_lwsp ... . ..... ..... .. &i imm=%uimm_6bit_lw rs1=2 %rd
138 lw 010 . ..... ..... 10 @c_lwsp
157 flw 011 . ..... ..... 10 @c_lwsp
|
| /dports/emulators/qemu-utils/qemu-4.2.1/target/riscv/ |
| H A D | insn16.decode | 66 @c_lwsp ... . ..... ..... .. &i imm=%uimm_6bit_lw rs1=2 %rd
119 lw 010 . ..... ..... 10 @c_lwsp
|
| H A D | insn16-32.decode | 27 flw 011 . ..... ..... 10 @c_lwsp
|
| /dports/emulators/qemu5/qemu-5.2.0/target/riscv/ |
| H A D | insn16.decode | 66 @c_lwsp ... . ..... ..... .. &i imm=%uimm_6bit_lw rs1=2 %rd
119 lw 010 . ..... ..... 10 @c_lwsp
|
| H A D | insn16-32.decode | 27 flw 011 . ..... ..... 10 @c_lwsp
|
| /dports/emulators/qemu-guest-agent/qemu-5.0.1/target/riscv/ |
| H A D | insn16.decode | 66 @c_lwsp ... . ..... ..... .. &i imm=%uimm_6bit_lw rs1=2 %rd
119 lw 010 . ..... ..... 10 @c_lwsp
|
| H A D | insn16-32.decode | 27 flw 011 . ..... ..... 10 @c_lwsp
|
| /dports/emulators/qemu42/qemu-4.2.1/target/riscv/ |
| H A D | insn16.decode | 66 @c_lwsp ... . ..... ..... .. &i imm=%uimm_6bit_lw rs1=2 %rd
119 lw 010 . ..... ..... 10 @c_lwsp
|
| H A D | insn16-32.decode | 27 flw 011 . ..... ..... 10 @c_lwsp
|
| /dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/target/riscv/ |
| H A D | insn16.decode | 66 @c_lwsp ... . ..... ..... .. &i imm=%uimm_6bit_lw rs1=2 %rd
119 lw 010 . ..... ..... 10 @c_lwsp
|
| H A D | insn16-32.decode | 27 flw 011 . ..... ..... 10 @c_lwsp
|
| /dports/emulators/qemu60/qemu-6.0.0/target/riscv/ |
| H A D | insn16.decode | 66 @c_lwsp ... . ..... ..... .. &i imm=%uimm_6bit_lw rs1=2 %rd
119 lw 010 . ..... ..... 10 @c_lwsp
|
| H A D | insn16-32.decode | 27 flw 011 . ..... ..... 10 @c_lwsp
|
| /dports/lang/v8/v8-9.6.180.12/test/cctest/ |
| H A D | test-disasm-riscv64.cc | 480 COMPARE(c_lwsp(s7, 244), "00005bde lw s7, 244(sp)"); in TEST()
|
| H A D | test-assembler-riscv64.cc | 1382 __ c_lwsp(a0, 40); in TEST() local
|
| /dports/emulators/riscv-isa-sim/riscv-isa-sim-4f12984/riscv/ |
| H A D | riscv.mk.in | 171 c_lwsp \
|
| /dports/devel/radare2/radare2-5.1.1/libr/asm/arch/riscv/ |
| H A D | riscv-opc.h | 1014 DECLARE_INSN(c_lwsp, MATCH_C_LWSP, MASK_C_LWSP)
|
| /dports/lang/sdcc/sdcc-4.0.0/support/sdbinutils/include/opcode/ |
| H A D | riscv-opc.h | 1068 DECLARE_INSN(c_lwsp, MATCH_C_LWSP, MASK_C_LWSP)
|
| /dports/devel/binutils/binutils-2.37/include/opcode/ |
| H A D | riscv-opc.h | 1148 DECLARE_INSN(c_lwsp, MATCH_C_LWSP, MASK_C_LWSP)
|
| /dports/devel/arm-elf-binutils/binutils-2.37/include/opcode/ |
| H A D | riscv-opc.h | 1148 DECLARE_INSN(c_lwsp, MATCH_C_LWSP, MASK_C_LWSP)
|
| /dports/devel/gnulibiberty/binutils-2.37/include/opcode/ |
| H A D | riscv-opc.h | 1148 DECLARE_INSN(c_lwsp, MATCH_C_LWSP, MASK_C_LWSP)
|
| /dports/devel/gdb/gdb-11.1/include/opcode/ |
| H A D | riscv-opc.h | 1148 DECLARE_INSN(c_lwsp, MATCH_C_LWSP, MASK_C_LWSP)
|
| /dports/emulators/riscv-isa-sim/riscv-isa-sim-4f12984/disasm/ |
| H A D | disasm.cc | 1064 DISASM_INSN("c.lwsp", c_lwsp, 0, {&xrd, &rvc_lwsp_address}); in disassembler_t()
|
| /dports/lang/v8/v8-9.6.180.12/src/codegen/riscv64/ |
| H A D | assembler-riscv64.h | 633 void c_lwsp(Register rd, uint16_t uimm8);
|