| /dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/target/riscv/ |
| H A D | insn16.decode | 67 @c_sdsp ... . ..... ..... .. &s imm=%uimm_6bit_sd rs1=2 rs2=%rs2_5
150 fsd 101 ...... ..... 10 @c_sdsp
160 sd 111 . ..... ..... 10 @c_sdsp
|
| /dports/emulators/qemu/qemu-6.2.0/target/riscv/ |
| H A D | insn16.decode | 67 @c_sdsp ... . ..... ..... .. &s imm=%uimm_6bit_sd rs1=2 rs2=%rs2_5
150 fsd 101 ...... ..... 10 @c_sdsp
160 sd 111 . ..... ..... 10 @c_sdsp
|
| /dports/emulators/qemu-utils/qemu-4.2.1/target/riscv/ |
| H A D | insn16.decode | 67 @c_sdsp ... . ..... ..... .. &s imm=%uimm_6bit_sd rs1=2 rs2=%rs2_5
131 fsd 101 ...... ..... 10 @c_sdsp
|
| H A D | insn16-64.decode | 36 sd 111 . ..... ..... 10 @c_sdsp
|
| /dports/emulators/qemu5/qemu-5.2.0/target/riscv/ |
| H A D | insn16.decode | 67 @c_sdsp ... . ..... ..... .. &s imm=%uimm_6bit_sd rs1=2 rs2=%rs2_5
131 fsd 101 ...... ..... 10 @c_sdsp
|
| H A D | insn16-64.decode | 36 sd 111 . ..... ..... 10 @c_sdsp
|
| /dports/emulators/qemu-guest-agent/qemu-5.0.1/target/riscv/ |
| H A D | insn16.decode | 67 @c_sdsp ... . ..... ..... .. &s imm=%uimm_6bit_sd rs1=2 rs2=%rs2_5
131 fsd 101 ...... ..... 10 @c_sdsp
|
| H A D | insn16-64.decode | 36 sd 111 . ..... ..... 10 @c_sdsp
|
| /dports/emulators/qemu42/qemu-4.2.1/target/riscv/ |
| H A D | insn16.decode | 67 @c_sdsp ... . ..... ..... .. &s imm=%uimm_6bit_sd rs1=2 rs2=%rs2_5
131 fsd 101 ...... ..... 10 @c_sdsp
|
| H A D | insn16-64.decode | 36 sd 111 . ..... ..... 10 @c_sdsp
|
| /dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/target/riscv/ |
| H A D | insn16.decode | 67 @c_sdsp ... . ..... ..... .. &s imm=%uimm_6bit_sd rs1=2 rs2=%rs2_5
131 fsd 101 ...... ..... 10 @c_sdsp
|
| H A D | insn16-64.decode | 36 sd 111 . ..... ..... 10 @c_sdsp
|
| /dports/emulators/qemu60/qemu-6.0.0/target/riscv/ |
| H A D | insn16.decode | 67 @c_sdsp ... . ..... ..... .. &s imm=%uimm_6bit_sd rs1=2 rs2=%rs2_5
131 fsd 101 ...... ..... 10 @c_sdsp
|
| H A D | insn16-64.decode | 36 sd 111 . ..... ..... 10 @c_sdsp
|
| /dports/lang/v8/v8-9.6.180.12/test/cctest/ |
| H A D | test-disasm-riscv64.cc | 497 COMPARE(c_sdsp(a4, 216), "0000edba sd a4, 216(sp)"); in TEST()
|
| H A D | test-assembler-riscv64.cc | 1390 __ c_sdsp(a0, 160); in TEST() local
|
| /dports/devel/radare2/radare2-5.1.1/libr/asm/arch/riscv/ |
| H A D | riscv-opc.h | 1030 DECLARE_INSN(c_sdsp, MATCH_C_SDSP, MASK_C_SDSP)
|
| /dports/lang/sdcc/sdcc-4.0.0/support/sdbinutils/include/opcode/ |
| H A D | riscv-opc.h | 1084 DECLARE_INSN(c_sdsp, MATCH_C_SDSP, MASK_C_SDSP)
|
| /dports/devel/binutils/binutils-2.37/include/opcode/ |
| H A D | riscv-opc.h | 1164 DECLARE_INSN(c_sdsp, MATCH_C_SDSP, MASK_C_SDSP)
|
| /dports/devel/arm-elf-binutils/binutils-2.37/include/opcode/ |
| H A D | riscv-opc.h | 1164 DECLARE_INSN(c_sdsp, MATCH_C_SDSP, MASK_C_SDSP)
|
| /dports/devel/gnulibiberty/binutils-2.37/include/opcode/ |
| H A D | riscv-opc.h | 1164 DECLARE_INSN(c_sdsp, MATCH_C_SDSP, MASK_C_SDSP)
|
| /dports/devel/gdb/gdb-11.1/include/opcode/ |
| H A D | riscv-opc.h | 1164 DECLARE_INSN(c_sdsp, MATCH_C_SDSP, MASK_C_SDSP)
|
| /dports/emulators/riscv-isa-sim/riscv-isa-sim-4f12984/disasm/ |
| H A D | disasm.cc | 1742 DISASM_INSN("c.sdsp", c_sdsp, 0, {&rvc_rs2, &rvc_sdsp_address}); in disassembler_t()
|
| /dports/lang/v8/v8-9.6.180.12/src/codegen/riscv64/ |
| H A D | assembler-riscv64.h | 649 void c_sdsp(Register rs2, uint16_t uimm9);
|
| /dports/devel/openocd/openocd-0.11.0/src/target/riscv/ |
| H A D | encoding.h | 2340 DECLARE_INSN(c_sdsp, MATCH_C_SDSP, MASK_C_SDSP)
|