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Searched refs:ce_clk (Results 1 – 25 of 71) sorted by relevance

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/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_fft/
H A Drfnoc_block_fft.v38 input wire ce_clk, port
128 .ce_clk (ce_clk ),
201 .ctrlport_clk (ce_clk),
273 .clk(ce_clk), .rst(ce_rst),
283 .clk(ce_clk), .reset(ce_rst),
290 .clk(ce_clk), .reset(ce_rst),
300 .clk(ce_clk), .reset(ce_rst),
310 .clk(ce_clk), .reset(ce_rst),
319 .clk(ce_clk), .reset(ce_rst),
326 always @(posedge ce_clk) begin
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H A Dnoc_shell_fft.v39 input wire ce_clk, port
160 .clk_b(ce_clk), .pulse_b (ce_rst_pulse)
164 .clk(ce_clk), .rst(1'b0),
172 assign ctrlport_clk = ce_clk;
225 assign axis_data_clk = ce_clk;
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_siggen/
H A Drfnoc_block_siggen.v41 input wire ce_clk, port
108 .ce_clk (ce_clk),
187 .ctrlport_clk (ce_clk),
221 .clk (ce_clk),
H A Dnoc_shell_siggen.v36 input wire ce_clk, port
144 .clk_b(ce_clk), .pulse_b (ce_rst_pulse)
148 .clk(ce_clk), .rst(1'b0),
156 assign ctrlport_clk = ce_clk;
209 assign axis_data_clk = ce_clk;
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_duc/
H A Drfnoc_block_duc.v35 input wire ce_clk, port
130 .ce_clk (ce_clk),
206 .ctrlport_clk (ce_clk),
297 .clk(ce_clk), .reset(ce_rst), .clear(clear_tx_seqnum[i]),
323 .clk(ce_clk), .reset(ce_rst), .clear(clear_tx_seqnum[i]), .clear_user(clear_user),
346 .clk(ce_clk), .reset(ce_rst), .clear(clear_duc),
H A Dnoc_shell_duc.v38 input wire ce_clk, port
158 .clk_b(ce_clk), .pulse_b (ce_rst_pulse)
162 .clk(ce_clk), .rst(1'b0),
170 assign ctrlport_clk = ce_clk;
223 assign axis_data_clk = ce_clk;
H A Drfnoc_block_duc_tb.sv53 bit ce_clk; register
57 sim_clock_gen #(DUC_CLK_PER) duc_clk_gen (.clk(ce_clk), .rst());
126 .ce_clk (ce_clk),
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_fosphor/
H A Drfnoc_block_fosphor.v50 input wire ce_clk, port
128 .ce_clk (ce_clk),
235 always @(posedge ce_clk) begin
332 always @(posedge ce_clk) begin
357 .clk (ce_clk),
H A Dnoc_shell_fosphor.v35 input wire ce_clk, port
165 .clk_b(ce_clk), .pulse_b (ce_rst_pulse)
169 .clk(ce_clk), .rst(1'b0),
177 assign ctrlport_clk = ce_clk;
230 assign axis_data_clk = ce_clk;
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_keep_one_in_n/
H A Drfnoc_block_keep_one_in_n.v36 input wire ce_clk, port
112 .ce_clk (ce_clk),
224 .clk (ce_clk),
237 .clk (ce_clk),
259 .clk (ce_clk),
H A Dnoc_shell_keep_one_in_n.v36 input wire ce_clk, port
155 .clk_b(ce_clk), .pulse_b (ce_rst_pulse)
159 .clk(ce_clk), .rst(1'b0),
167 assign ctrlport_clk = ce_clk;
220 assign axis_data_clk = ce_clk;
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_vector_iir/
H A Drfnoc_block_vector_iir.v45 input wire ce_clk, port
133 .ce_clk (ce_clk),
230 .ctrlport_clk (ce_clk),
316 always @(posedge ce_clk) begin
379 .clk (ce_clk),
H A Dnoc_shell_vector_iir.v36 input wire ce_clk, port
157 .clk_b(ce_clk), .pulse_b (ce_rst_pulse)
161 .clk(ce_clk), .rst(1'b0),
169 assign ctrlport_clk = ce_clk;
222 assign axis_data_clk = ce_clk;
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_moving_avg/
H A Drfnoc_block_moving_avg.v38 input wire ce_clk, port
123 .ce_clk (ce_clk),
223 .ctrlport_clk (ce_clk),
257 .clk (ce_clk),
H A Dnoc_shell_moving_avg.v36 input wire ce_clk, port
157 .clk_b(ce_clk), .pulse_b (ce_rst_pulse)
161 .clk(ce_clk), .rst(1'b0),
169 assign ctrlport_clk = ce_clk;
222 assign axis_data_clk = ce_clk;
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_window/
H A Drfnoc_block_window.v45 input wire ce_clk, port
126 .ce_clk (ce_clk),
226 .ctrlport_clk (ce_clk),
262 .clk (ce_clk),
H A Dnoc_shell_window.v37 input wire ce_clk, port
158 .clk_b(ce_clk), .pulse_b (ce_rst_pulse)
162 .clk(ce_clk), .rst(1'b0),
170 assign ctrlport_clk = ce_clk;
223 assign axis_data_clk = ce_clk;
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_ddc/
H A Drfnoc_block_ddc.v35 input wire ce_clk, port
130 .ce_clk (ce_clk),
207 .ctrlport_clk (ce_clk),
302 .clk(ce_clk),
341 .clk(ce_clk), .reset(ce_rst), .clear(clear_tx_seqnum[i]), .clear_user(clear_user),
374 .clk(ce_clk), .reset(ce_rst),
H A Dnoc_shell_ddc.v38 input wire ce_clk, port
158 .clk_b(ce_clk), .pulse_b (ce_rst_pulse)
162 .clk(ce_clk), .rst(1'b0),
170 assign ctrlport_clk = ce_clk;
223 assign axis_data_clk = ce_clk;
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_fir_filter/
H A Drfnoc_block_fir_filter.v69 input wire ce_clk, port
164 .ce_clk (ce_clk),
246 .ctrlport_clk (ce_clk),
287 .clk (ce_clk),
H A Dnoc_shell_fir_filter.v43 input wire ce_clk, port
164 .clk_b(ce_clk), .pulse_b (ce_rst_pulse)
168 .clk(ce_clk), .rst(1'b0),
176 assign ctrlport_clk = ce_clk;
229 assign axis_data_clk = ce_clk;
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_logpwr/
H A Drfnoc_block_logpwr.v40 input wire ce_clk, port
114 .ce_clk (ce_clk),
231 .clk (ce_clk),
H A Dnoc_shell_logpwr.v36 input wire ce_clk, port
146 .clk_b(ce_clk), .pulse_b (ce_rst_pulse)
150 .clk(ce_clk), .rst(1'b0),
170 assign axis_data_clk = ce_clk;
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_addsub/
H A Dnoc_shell_addsub.v37 input wire ce_clk, port
171 .clk_b(ce_clk), .pulse_b (ce_rst_pulse)
175 .clk(ce_clk), .rst(1'b0),
195 assign axis_data_clk = ce_clk;
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/
H A Dnoc_traffic_counter.v12 input ce_clk, input ce_rst, port
63 .reset(ce_rst), .i_aclk(ce_clk),
71 .o_aclk(ce_clk),

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