Searched refs:clk_sig (Results 1 – 6 of 6) sorted by relevance
/dports/devel/nextpnr/nextpnr-48cd407/ecp5/ |
H A D | arch_place.cc | 40 IdString clk_sig, lsr_sig; in slicesCompatible() local 46 clk_sig = cell->sliceInfo.clk_sig; in slicesCompatible() 52 if (cell->sliceInfo.clk_sig != clk_sig) in slicesCompatible()
|
H A D | archdefs.h | 177 IdString clk_sig, lsr_sig, clkmux, lsrmux, srmode; member
|
H A D | pack.cc | 3013 ci->sliceInfo.clk_sig = ci->ports[id_CLK].net->name; in assignArchInfo() 3015 ci->sliceInfo.clk_sig = IdString(); in assignArchInfo()
|
/dports/cad/ghdl/ghdl-1.0.0/testsuite/gna/issue332/ |
H A D | irqc_tb.vhd | 25 SIGNAL clk_sig: std_logic; signal 63 clk => clk_sig, 75 clk_gen(clk_sig, 50.0E6, 0 fs, run_sig); -- 50 MHz clock
|
/dports/cad/yosys/yosys-yosys-0.12/passes/techmap/ |
H A D | abc.cc | 121 RTLIL::SigSpec clk_sig, en_sig; variable 172 if (clk_sig != assign_map(cell->getPort(ID::C))) in extract_cell() 675 clk_sig = RTLIL::SigSpec(); in abc_module() 702 if (dff_mode && clk_sig.empty()) in abc_module() 786 if (clk_sig.size() == 0) in abc_module() 808 if (clk_sig.size() != 0) in abc_module() 809 mark_port(clk_sig); in abc_module() 1151 log_assert(clk_sig.size() == 1); in abc_module() 1165 cell->setPort(ID::C, clk_sig); in abc_module() 1182 log_assert(clk_sig.size() == 1); in abc_module() [all …]
|
/dports/cad/yosys/yosys-yosys-0.12/frontends/liberty/ |
H A D | liberty.cc | 222 RTLIL::SigSpec clk_sig, data_sig, clear_sig, preset_sig; in create_ff() local 227 clk_sig = parse_func_expr(module, child->value.c_str()); in create_ff() 236 if (clk_sig.size() == 0 || data_sig.size() == 0) in create_ff() 244 if (it.second->type == ID($_NOT_) && it.second->getPort(ID::Y) == clk_sig) { in create_ff() 245 clk_sig = it.second->getPort(ID::A); in create_ff() 269 cell->setPort(ID::C, clk_sig); in create_ff()
|