| /dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/drivers/video/nexell/soc/ |
| H A D | s5pxx18_soc_disptop_clk.c | 83 regvalue = pregister->clkenb; in nx_disp_top_clkgen_set_clock_bclk_mode()
87 writel(regvalue, &pregister->clkenb); in nx_disp_top_clkgen_set_clock_bclk_mode()
96 mode = (pregister->clkenb & 3ul); in nx_disp_top_clkgen_get_clock_bclk_mode()
131 regvalue = pregister->clkenb; in nx_disp_top_clkgen_set_clock_pclk_mode()
135 writel(regvalue, &pregister->clkenb); in nx_disp_top_clkgen_set_clock_pclk_mode()
218 read_value = pregister->clkenb; in nx_disp_top_clkgen_set_clock_divisor_enable()
222 writel(read_value, &pregister->clkenb); in nx_disp_top_clkgen_set_clock_divisor_enable()
233 return (int)((pregister->clkenb & in nx_disp_top_clkgen_get_clock_divisor_enable()
276 read_value = pregister->clkenb; in nx_disp_top_clkgen_set_input_inv()
280 writel(read_value, &pregister->clkenb); in nx_disp_top_clkgen_set_input_inv()
[all …]
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| /dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/drivers/video/nexell/soc/ |
| H A D | s5pxx18_soc_disptop_clk.c | 83 regvalue = pregister->clkenb; in nx_disp_top_clkgen_set_clock_bclk_mode()
87 writel(regvalue, &pregister->clkenb); in nx_disp_top_clkgen_set_clock_bclk_mode()
96 mode = (pregister->clkenb & 3ul); in nx_disp_top_clkgen_get_clock_bclk_mode()
131 regvalue = pregister->clkenb; in nx_disp_top_clkgen_set_clock_pclk_mode()
135 writel(regvalue, &pregister->clkenb); in nx_disp_top_clkgen_set_clock_pclk_mode()
218 read_value = pregister->clkenb; in nx_disp_top_clkgen_set_clock_divisor_enable()
222 writel(read_value, &pregister->clkenb); in nx_disp_top_clkgen_set_clock_divisor_enable()
233 return (int)((pregister->clkenb & in nx_disp_top_clkgen_get_clock_divisor_enable()
276 read_value = pregister->clkenb; in nx_disp_top_clkgen_set_input_inv()
280 writel(read_value, &pregister->clkenb); in nx_disp_top_clkgen_set_input_inv()
[all …]
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| /dports/sysutils/u-boot-chip/u-boot-2021.07/drivers/video/nexell/soc/ |
| H A D | s5pxx18_soc_disptop_clk.c | 83 regvalue = pregister->clkenb; in nx_disp_top_clkgen_set_clock_bclk_mode()
87 writel(regvalue, &pregister->clkenb); in nx_disp_top_clkgen_set_clock_bclk_mode()
96 mode = (pregister->clkenb & 3ul); in nx_disp_top_clkgen_get_clock_bclk_mode()
131 regvalue = pregister->clkenb; in nx_disp_top_clkgen_set_clock_pclk_mode()
135 writel(regvalue, &pregister->clkenb); in nx_disp_top_clkgen_set_clock_pclk_mode()
218 read_value = pregister->clkenb; in nx_disp_top_clkgen_set_clock_divisor_enable()
222 writel(read_value, &pregister->clkenb); in nx_disp_top_clkgen_set_clock_divisor_enable()
233 return (int)((pregister->clkenb & in nx_disp_top_clkgen_get_clock_divisor_enable()
276 read_value = pregister->clkenb; in nx_disp_top_clkgen_set_input_inv()
280 writel(read_value, &pregister->clkenb); in nx_disp_top_clkgen_set_input_inv()
[all …]
|
| /dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/drivers/video/nexell/soc/ |
| H A D | s5pxx18_soc_disptop_clk.c | 83 regvalue = pregister->clkenb; in nx_disp_top_clkgen_set_clock_bclk_mode()
87 writel(regvalue, &pregister->clkenb); in nx_disp_top_clkgen_set_clock_bclk_mode()
96 mode = (pregister->clkenb & 3ul); in nx_disp_top_clkgen_get_clock_bclk_mode()
131 regvalue = pregister->clkenb; in nx_disp_top_clkgen_set_clock_pclk_mode()
135 writel(regvalue, &pregister->clkenb); in nx_disp_top_clkgen_set_clock_pclk_mode()
218 read_value = pregister->clkenb; in nx_disp_top_clkgen_set_clock_divisor_enable()
222 writel(read_value, &pregister->clkenb); in nx_disp_top_clkgen_set_clock_divisor_enable()
233 return (int)((pregister->clkenb & in nx_disp_top_clkgen_get_clock_divisor_enable()
276 read_value = pregister->clkenb; in nx_disp_top_clkgen_set_input_inv()
280 writel(read_value, &pregister->clkenb); in nx_disp_top_clkgen_set_input_inv()
[all …]
|
| /dports/sysutils/u-boot-firefly-rk3399/u-boot-2021.07/drivers/video/nexell/soc/ |
| H A D | s5pxx18_soc_disptop_clk.c | 83 regvalue = pregister->clkenb; in nx_disp_top_clkgen_set_clock_bclk_mode()
87 writel(regvalue, &pregister->clkenb); in nx_disp_top_clkgen_set_clock_bclk_mode()
96 mode = (pregister->clkenb & 3ul); in nx_disp_top_clkgen_get_clock_bclk_mode()
131 regvalue = pregister->clkenb; in nx_disp_top_clkgen_set_clock_pclk_mode()
135 writel(regvalue, &pregister->clkenb); in nx_disp_top_clkgen_set_clock_pclk_mode()
218 read_value = pregister->clkenb; in nx_disp_top_clkgen_set_clock_divisor_enable()
222 writel(read_value, &pregister->clkenb); in nx_disp_top_clkgen_set_clock_divisor_enable()
233 return (int)((pregister->clkenb & in nx_disp_top_clkgen_get_clock_divisor_enable()
276 read_value = pregister->clkenb; in nx_disp_top_clkgen_set_input_inv()
280 writel(read_value, &pregister->clkenb); in nx_disp_top_clkgen_set_input_inv()
[all …]
|
| /dports/sysutils/u-boot-a13-olinuxino/u-boot-2021.07/drivers/video/nexell/soc/ |
| H A D | s5pxx18_soc_disptop_clk.c | 83 regvalue = pregister->clkenb; in nx_disp_top_clkgen_set_clock_bclk_mode()
87 writel(regvalue, &pregister->clkenb); in nx_disp_top_clkgen_set_clock_bclk_mode()
96 mode = (pregister->clkenb & 3ul); in nx_disp_top_clkgen_get_clock_bclk_mode()
131 regvalue = pregister->clkenb; in nx_disp_top_clkgen_set_clock_pclk_mode()
135 writel(regvalue, &pregister->clkenb); in nx_disp_top_clkgen_set_clock_pclk_mode()
218 read_value = pregister->clkenb; in nx_disp_top_clkgen_set_clock_divisor_enable()
222 writel(read_value, &pregister->clkenb); in nx_disp_top_clkgen_set_clock_divisor_enable()
233 return (int)((pregister->clkenb & in nx_disp_top_clkgen_get_clock_divisor_enable()
276 read_value = pregister->clkenb; in nx_disp_top_clkgen_set_input_inv()
280 writel(read_value, &pregister->clkenb); in nx_disp_top_clkgen_set_input_inv()
[all …]
|
| /dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/drivers/video/nexell/soc/ |
| H A D | s5pxx18_soc_disptop_clk.c | 83 regvalue = pregister->clkenb; in nx_disp_top_clkgen_set_clock_bclk_mode()
87 writel(regvalue, &pregister->clkenb); in nx_disp_top_clkgen_set_clock_bclk_mode()
96 mode = (pregister->clkenb & 3ul); in nx_disp_top_clkgen_get_clock_bclk_mode()
131 regvalue = pregister->clkenb; in nx_disp_top_clkgen_set_clock_pclk_mode()
135 writel(regvalue, &pregister->clkenb); in nx_disp_top_clkgen_set_clock_pclk_mode()
218 read_value = pregister->clkenb; in nx_disp_top_clkgen_set_clock_divisor_enable()
222 writel(read_value, &pregister->clkenb); in nx_disp_top_clkgen_set_clock_divisor_enable()
233 return (int)((pregister->clkenb & in nx_disp_top_clkgen_get_clock_divisor_enable()
276 read_value = pregister->clkenb; in nx_disp_top_clkgen_set_input_inv()
280 writel(read_value, &pregister->clkenb); in nx_disp_top_clkgen_set_input_inv()
[all …]
|
| /dports/sysutils/u-boot-sopine/u-boot-2021.07/drivers/video/nexell/soc/ |
| H A D | s5pxx18_soc_disptop_clk.c | 83 regvalue = pregister->clkenb; in nx_disp_top_clkgen_set_clock_bclk_mode()
87 writel(regvalue, &pregister->clkenb); in nx_disp_top_clkgen_set_clock_bclk_mode()
96 mode = (pregister->clkenb & 3ul); in nx_disp_top_clkgen_get_clock_bclk_mode()
131 regvalue = pregister->clkenb; in nx_disp_top_clkgen_set_clock_pclk_mode()
135 writel(regvalue, &pregister->clkenb); in nx_disp_top_clkgen_set_clock_pclk_mode()
218 read_value = pregister->clkenb; in nx_disp_top_clkgen_set_clock_divisor_enable()
222 writel(read_value, &pregister->clkenb); in nx_disp_top_clkgen_set_clock_divisor_enable()
233 return (int)((pregister->clkenb & in nx_disp_top_clkgen_get_clock_divisor_enable()
276 read_value = pregister->clkenb; in nx_disp_top_clkgen_set_input_inv()
280 writel(read_value, &pregister->clkenb); in nx_disp_top_clkgen_set_input_inv()
[all …]
|
| /dports/sysutils/u-boot-rpi/u-boot-2021.07/drivers/video/nexell/soc/ |
| H A D | s5pxx18_soc_disptop_clk.c | 83 regvalue = pregister->clkenb; in nx_disp_top_clkgen_set_clock_bclk_mode()
87 writel(regvalue, &pregister->clkenb); in nx_disp_top_clkgen_set_clock_bclk_mode()
96 mode = (pregister->clkenb & 3ul); in nx_disp_top_clkgen_get_clock_bclk_mode()
131 regvalue = pregister->clkenb; in nx_disp_top_clkgen_set_clock_pclk_mode()
135 writel(regvalue, &pregister->clkenb); in nx_disp_top_clkgen_set_clock_pclk_mode()
218 read_value = pregister->clkenb; in nx_disp_top_clkgen_set_clock_divisor_enable()
222 writel(read_value, &pregister->clkenb); in nx_disp_top_clkgen_set_clock_divisor_enable()
233 return (int)((pregister->clkenb & in nx_disp_top_clkgen_get_clock_divisor_enable()
276 read_value = pregister->clkenb; in nx_disp_top_clkgen_set_input_inv()
280 writel(read_value, &pregister->clkenb); in nx_disp_top_clkgen_set_input_inv()
[all …]
|
| /dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/drivers/video/nexell/soc/ |
| H A D | s5pxx18_soc_disptop_clk.c | 83 regvalue = pregister->clkenb; in nx_disp_top_clkgen_set_clock_bclk_mode()
87 writel(regvalue, &pregister->clkenb); in nx_disp_top_clkgen_set_clock_bclk_mode()
96 mode = (pregister->clkenb & 3ul); in nx_disp_top_clkgen_get_clock_bclk_mode()
131 regvalue = pregister->clkenb; in nx_disp_top_clkgen_set_clock_pclk_mode()
135 writel(regvalue, &pregister->clkenb); in nx_disp_top_clkgen_set_clock_pclk_mode()
218 read_value = pregister->clkenb; in nx_disp_top_clkgen_set_clock_divisor_enable()
222 writel(read_value, &pregister->clkenb); in nx_disp_top_clkgen_set_clock_divisor_enable()
233 return (int)((pregister->clkenb & in nx_disp_top_clkgen_get_clock_divisor_enable()
276 read_value = pregister->clkenb; in nx_disp_top_clkgen_set_input_inv()
280 writel(read_value, &pregister->clkenb); in nx_disp_top_clkgen_set_input_inv()
[all …]
|
| /dports/sysutils/u-boot-pinebookpro/u-boot-2021.07/drivers/video/nexell/soc/ |
| H A D | s5pxx18_soc_disptop_clk.c | 83 regvalue = pregister->clkenb; in nx_disp_top_clkgen_set_clock_bclk_mode()
87 writel(regvalue, &pregister->clkenb); in nx_disp_top_clkgen_set_clock_bclk_mode()
96 mode = (pregister->clkenb & 3ul); in nx_disp_top_clkgen_get_clock_bclk_mode()
131 regvalue = pregister->clkenb; in nx_disp_top_clkgen_set_clock_pclk_mode()
135 writel(regvalue, &pregister->clkenb); in nx_disp_top_clkgen_set_clock_pclk_mode()
218 read_value = pregister->clkenb; in nx_disp_top_clkgen_set_clock_divisor_enable()
222 writel(read_value, &pregister->clkenb); in nx_disp_top_clkgen_set_clock_divisor_enable()
233 return (int)((pregister->clkenb & in nx_disp_top_clkgen_get_clock_divisor_enable()
276 read_value = pregister->clkenb; in nx_disp_top_clkgen_set_input_inv()
280 writel(read_value, &pregister->clkenb); in nx_disp_top_clkgen_set_input_inv()
[all …]
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| /dports/sysutils/u-boot-nanopi-neo2/u-boot-2021.07/drivers/video/nexell/soc/ |
| H A D | s5pxx18_soc_disptop_clk.c | 83 regvalue = pregister->clkenb; in nx_disp_top_clkgen_set_clock_bclk_mode()
87 writel(regvalue, &pregister->clkenb); in nx_disp_top_clkgen_set_clock_bclk_mode()
96 mode = (pregister->clkenb & 3ul); in nx_disp_top_clkgen_get_clock_bclk_mode()
131 regvalue = pregister->clkenb; in nx_disp_top_clkgen_set_clock_pclk_mode()
135 writel(regvalue, &pregister->clkenb); in nx_disp_top_clkgen_set_clock_pclk_mode()
218 read_value = pregister->clkenb; in nx_disp_top_clkgen_set_clock_divisor_enable()
222 writel(read_value, &pregister->clkenb); in nx_disp_top_clkgen_set_clock_divisor_enable()
233 return (int)((pregister->clkenb & in nx_disp_top_clkgen_get_clock_divisor_enable()
276 read_value = pregister->clkenb; in nx_disp_top_clkgen_set_input_inv()
280 writel(read_value, &pregister->clkenb); in nx_disp_top_clkgen_set_input_inv()
[all …]
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| /dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/drivers/video/nexell/soc/ |
| H A D | s5pxx18_soc_disptop_clk.c | 83 regvalue = pregister->clkenb; in nx_disp_top_clkgen_set_clock_bclk_mode()
87 writel(regvalue, &pregister->clkenb); in nx_disp_top_clkgen_set_clock_bclk_mode()
96 mode = (pregister->clkenb & 3ul); in nx_disp_top_clkgen_get_clock_bclk_mode()
131 regvalue = pregister->clkenb; in nx_disp_top_clkgen_set_clock_pclk_mode()
135 writel(regvalue, &pregister->clkenb); in nx_disp_top_clkgen_set_clock_pclk_mode()
218 read_value = pregister->clkenb; in nx_disp_top_clkgen_set_clock_divisor_enable()
222 writel(read_value, &pregister->clkenb); in nx_disp_top_clkgen_set_clock_divisor_enable()
233 return (int)((pregister->clkenb & in nx_disp_top_clkgen_get_clock_divisor_enable()
276 read_value = pregister->clkenb; in nx_disp_top_clkgen_set_input_inv()
280 writel(read_value, &pregister->clkenb); in nx_disp_top_clkgen_set_input_inv()
[all …]
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| /dports/sysutils/u-boot-nanopi-m1plus/u-boot-2021.07/drivers/video/nexell/soc/ |
| H A D | s5pxx18_soc_disptop_clk.c | 83 regvalue = pregister->clkenb; in nx_disp_top_clkgen_set_clock_bclk_mode()
87 writel(regvalue, &pregister->clkenb); in nx_disp_top_clkgen_set_clock_bclk_mode()
96 mode = (pregister->clkenb & 3ul); in nx_disp_top_clkgen_get_clock_bclk_mode()
131 regvalue = pregister->clkenb; in nx_disp_top_clkgen_set_clock_pclk_mode()
135 writel(regvalue, &pregister->clkenb); in nx_disp_top_clkgen_set_clock_pclk_mode()
218 read_value = pregister->clkenb; in nx_disp_top_clkgen_set_clock_divisor_enable()
222 writel(read_value, &pregister->clkenb); in nx_disp_top_clkgen_set_clock_divisor_enable()
233 return (int)((pregister->clkenb & in nx_disp_top_clkgen_get_clock_divisor_enable()
276 read_value = pregister->clkenb; in nx_disp_top_clkgen_set_input_inv()
280 writel(read_value, &pregister->clkenb); in nx_disp_top_clkgen_set_input_inv()
[all …]
|
| /dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/drivers/video/nexell/soc/ |
| H A D | s5pxx18_soc_disptop_clk.c | 83 regvalue = pregister->clkenb; in nx_disp_top_clkgen_set_clock_bclk_mode()
87 writel(regvalue, &pregister->clkenb); in nx_disp_top_clkgen_set_clock_bclk_mode()
96 mode = (pregister->clkenb & 3ul); in nx_disp_top_clkgen_get_clock_bclk_mode()
131 regvalue = pregister->clkenb; in nx_disp_top_clkgen_set_clock_pclk_mode()
135 writel(regvalue, &pregister->clkenb); in nx_disp_top_clkgen_set_clock_pclk_mode()
218 read_value = pregister->clkenb; in nx_disp_top_clkgen_set_clock_divisor_enable()
222 writel(read_value, &pregister->clkenb); in nx_disp_top_clkgen_set_clock_divisor_enable()
233 return (int)((pregister->clkenb & in nx_disp_top_clkgen_get_clock_divisor_enable()
276 read_value = pregister->clkenb; in nx_disp_top_clkgen_set_input_inv()
280 writel(read_value, &pregister->clkenb); in nx_disp_top_clkgen_set_input_inv()
[all …]
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| /dports/sysutils/u-boot-clearfog/u-boot-2021.07/drivers/video/nexell/soc/ |
| H A D | s5pxx18_soc_disptop_clk.c | 83 regvalue = pregister->clkenb; in nx_disp_top_clkgen_set_clock_bclk_mode()
87 writel(regvalue, &pregister->clkenb); in nx_disp_top_clkgen_set_clock_bclk_mode()
96 mode = (pregister->clkenb & 3ul); in nx_disp_top_clkgen_get_clock_bclk_mode()
131 regvalue = pregister->clkenb; in nx_disp_top_clkgen_set_clock_pclk_mode()
135 writel(regvalue, &pregister->clkenb); in nx_disp_top_clkgen_set_clock_pclk_mode()
218 read_value = pregister->clkenb; in nx_disp_top_clkgen_set_clock_divisor_enable()
222 writel(read_value, &pregister->clkenb); in nx_disp_top_clkgen_set_clock_divisor_enable()
233 return (int)((pregister->clkenb & in nx_disp_top_clkgen_get_clock_divisor_enable()
276 read_value = pregister->clkenb; in nx_disp_top_clkgen_set_input_inv()
280 writel(read_value, &pregister->clkenb); in nx_disp_top_clkgen_set_input_inv()
[all …]
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| /dports/sysutils/u-boot-cubieboard/u-boot-2021.07/drivers/video/nexell/soc/ |
| H A D | s5pxx18_soc_disptop_clk.c | 83 regvalue = pregister->clkenb; in nx_disp_top_clkgen_set_clock_bclk_mode()
87 writel(regvalue, &pregister->clkenb); in nx_disp_top_clkgen_set_clock_bclk_mode()
96 mode = (pregister->clkenb & 3ul); in nx_disp_top_clkgen_get_clock_bclk_mode()
131 regvalue = pregister->clkenb; in nx_disp_top_clkgen_set_clock_pclk_mode()
135 writel(regvalue, &pregister->clkenb); in nx_disp_top_clkgen_set_clock_pclk_mode()
218 read_value = pregister->clkenb; in nx_disp_top_clkgen_set_clock_divisor_enable()
222 writel(read_value, &pregister->clkenb); in nx_disp_top_clkgen_set_clock_divisor_enable()
233 return (int)((pregister->clkenb & in nx_disp_top_clkgen_get_clock_divisor_enable()
276 read_value = pregister->clkenb; in nx_disp_top_clkgen_set_input_inv()
280 writel(read_value, &pregister->clkenb); in nx_disp_top_clkgen_set_input_inv()
[all …]
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| /dports/sysutils/u-boot-orangepi-zero-plus/u-boot-2021.07/drivers/video/nexell/soc/ |
| H A D | s5pxx18_soc_disptop_clk.c | 83 regvalue = pregister->clkenb; in nx_disp_top_clkgen_set_clock_bclk_mode()
87 writel(regvalue, &pregister->clkenb); in nx_disp_top_clkgen_set_clock_bclk_mode()
96 mode = (pregister->clkenb & 3ul); in nx_disp_top_clkgen_get_clock_bclk_mode()
131 regvalue = pregister->clkenb; in nx_disp_top_clkgen_set_clock_pclk_mode()
135 writel(regvalue, &pregister->clkenb); in nx_disp_top_clkgen_set_clock_pclk_mode()
218 read_value = pregister->clkenb; in nx_disp_top_clkgen_set_clock_divisor_enable()
222 writel(read_value, &pregister->clkenb); in nx_disp_top_clkgen_set_clock_divisor_enable()
233 return (int)((pregister->clkenb & in nx_disp_top_clkgen_get_clock_divisor_enable()
276 read_value = pregister->clkenb; in nx_disp_top_clkgen_set_input_inv()
280 writel(read_value, &pregister->clkenb); in nx_disp_top_clkgen_set_input_inv()
[all …]
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| /dports/sysutils/u-boot-orangepi-r1/u-boot-2021.07/drivers/video/nexell/soc/ |
| H A D | s5pxx18_soc_disptop_clk.c | 83 regvalue = pregister->clkenb; in nx_disp_top_clkgen_set_clock_bclk_mode()
87 writel(regvalue, &pregister->clkenb); in nx_disp_top_clkgen_set_clock_bclk_mode()
96 mode = (pregister->clkenb & 3ul); in nx_disp_top_clkgen_get_clock_bclk_mode()
131 regvalue = pregister->clkenb; in nx_disp_top_clkgen_set_clock_pclk_mode()
135 writel(regvalue, &pregister->clkenb); in nx_disp_top_clkgen_set_clock_pclk_mode()
218 read_value = pregister->clkenb; in nx_disp_top_clkgen_set_clock_divisor_enable()
222 writel(read_value, &pregister->clkenb); in nx_disp_top_clkgen_set_clock_divisor_enable()
233 return (int)((pregister->clkenb & in nx_disp_top_clkgen_get_clock_divisor_enable()
276 read_value = pregister->clkenb; in nx_disp_top_clkgen_set_input_inv()
280 writel(read_value, &pregister->clkenb); in nx_disp_top_clkgen_set_input_inv()
[all …]
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| /dports/sysutils/u-boot-orangepi-zero/u-boot-2021.07/drivers/video/nexell/soc/ |
| H A D | s5pxx18_soc_disptop_clk.c | 83 regvalue = pregister->clkenb; in nx_disp_top_clkgen_set_clock_bclk_mode()
87 writel(regvalue, &pregister->clkenb); in nx_disp_top_clkgen_set_clock_bclk_mode()
96 mode = (pregister->clkenb & 3ul); in nx_disp_top_clkgen_get_clock_bclk_mode()
131 regvalue = pregister->clkenb; in nx_disp_top_clkgen_set_clock_pclk_mode()
135 writel(regvalue, &pregister->clkenb); in nx_disp_top_clkgen_set_clock_pclk_mode()
218 read_value = pregister->clkenb; in nx_disp_top_clkgen_set_clock_divisor_enable()
222 writel(read_value, &pregister->clkenb); in nx_disp_top_clkgen_set_clock_divisor_enable()
233 return (int)((pregister->clkenb & in nx_disp_top_clkgen_get_clock_divisor_enable()
276 read_value = pregister->clkenb; in nx_disp_top_clkgen_set_input_inv()
280 writel(read_value, &pregister->clkenb); in nx_disp_top_clkgen_set_input_inv()
[all …]
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| /dports/sysutils/u-boot-pandaboard/u-boot-2021.07/drivers/video/nexell/soc/ |
| H A D | s5pxx18_soc_disptop_clk.c | 83 regvalue = pregister->clkenb; in nx_disp_top_clkgen_set_clock_bclk_mode()
87 writel(regvalue, &pregister->clkenb); in nx_disp_top_clkgen_set_clock_bclk_mode()
96 mode = (pregister->clkenb & 3ul); in nx_disp_top_clkgen_get_clock_bclk_mode()
131 regvalue = pregister->clkenb; in nx_disp_top_clkgen_set_clock_pclk_mode()
135 writel(regvalue, &pregister->clkenb); in nx_disp_top_clkgen_set_clock_pclk_mode()
218 read_value = pregister->clkenb; in nx_disp_top_clkgen_set_clock_divisor_enable()
222 writel(read_value, &pregister->clkenb); in nx_disp_top_clkgen_set_clock_divisor_enable()
233 return (int)((pregister->clkenb & in nx_disp_top_clkgen_get_clock_divisor_enable()
276 read_value = pregister->clkenb; in nx_disp_top_clkgen_set_input_inv()
280 writel(read_value, &pregister->clkenb); in nx_disp_top_clkgen_set_input_inv()
[all …]
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| /dports/sysutils/u-boot-pine64/u-boot-2021.07/drivers/video/nexell/soc/ |
| H A D | s5pxx18_soc_disptop_clk.c | 83 regvalue = pregister->clkenb; in nx_disp_top_clkgen_set_clock_bclk_mode()
87 writel(regvalue, &pregister->clkenb); in nx_disp_top_clkgen_set_clock_bclk_mode()
96 mode = (pregister->clkenb & 3ul); in nx_disp_top_clkgen_get_clock_bclk_mode()
131 regvalue = pregister->clkenb; in nx_disp_top_clkgen_set_clock_pclk_mode()
135 writel(regvalue, &pregister->clkenb); in nx_disp_top_clkgen_set_clock_pclk_mode()
218 read_value = pregister->clkenb; in nx_disp_top_clkgen_set_clock_divisor_enable()
222 writel(read_value, &pregister->clkenb); in nx_disp_top_clkgen_set_clock_divisor_enable()
233 return (int)((pregister->clkenb & in nx_disp_top_clkgen_get_clock_divisor_enable()
276 read_value = pregister->clkenb; in nx_disp_top_clkgen_set_input_inv()
280 writel(read_value, &pregister->clkenb); in nx_disp_top_clkgen_set_input_inv()
[all …]
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| /dports/sysutils/u-boot-pine-h64/u-boot-2021.07/drivers/video/nexell/soc/ |
| H A D | s5pxx18_soc_disptop_clk.c | 83 regvalue = pregister->clkenb; in nx_disp_top_clkgen_set_clock_bclk_mode()
87 writel(regvalue, &pregister->clkenb); in nx_disp_top_clkgen_set_clock_bclk_mode()
96 mode = (pregister->clkenb & 3ul); in nx_disp_top_clkgen_get_clock_bclk_mode()
131 regvalue = pregister->clkenb; in nx_disp_top_clkgen_set_clock_pclk_mode()
135 writel(regvalue, &pregister->clkenb); in nx_disp_top_clkgen_set_clock_pclk_mode()
218 read_value = pregister->clkenb; in nx_disp_top_clkgen_set_clock_divisor_enable()
222 writel(read_value, &pregister->clkenb); in nx_disp_top_clkgen_set_clock_divisor_enable()
233 return (int)((pregister->clkenb & in nx_disp_top_clkgen_get_clock_divisor_enable()
276 read_value = pregister->clkenb; in nx_disp_top_clkgen_set_input_inv()
280 writel(read_value, &pregister->clkenb); in nx_disp_top_clkgen_set_input_inv()
[all …]
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| /dports/sysutils/u-boot-pcduino3/u-boot-2021.07/drivers/video/nexell/soc/ |
| H A D | s5pxx18_soc_disptop_clk.c | 83 regvalue = pregister->clkenb; in nx_disp_top_clkgen_set_clock_bclk_mode()
87 writel(regvalue, &pregister->clkenb); in nx_disp_top_clkgen_set_clock_bclk_mode()
96 mode = (pregister->clkenb & 3ul); in nx_disp_top_clkgen_get_clock_bclk_mode()
131 regvalue = pregister->clkenb; in nx_disp_top_clkgen_set_clock_pclk_mode()
135 writel(regvalue, &pregister->clkenb); in nx_disp_top_clkgen_set_clock_pclk_mode()
218 read_value = pregister->clkenb; in nx_disp_top_clkgen_set_clock_divisor_enable()
222 writel(read_value, &pregister->clkenb); in nx_disp_top_clkgen_set_clock_divisor_enable()
233 return (int)((pregister->clkenb & in nx_disp_top_clkgen_get_clock_divisor_enable()
276 read_value = pregister->clkenb; in nx_disp_top_clkgen_set_input_inv()
280 writel(read_value, &pregister->clkenb); in nx_disp_top_clkgen_set_input_inv()
[all …]
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| /dports/sysutils/u-boot-pine64-lts/u-boot-2021.07/drivers/video/nexell/soc/ |
| H A D | s5pxx18_soc_disptop_clk.c | 83 regvalue = pregister->clkenb; in nx_disp_top_clkgen_set_clock_bclk_mode()
87 writel(regvalue, &pregister->clkenb); in nx_disp_top_clkgen_set_clock_bclk_mode()
96 mode = (pregister->clkenb & 3ul); in nx_disp_top_clkgen_get_clock_bclk_mode()
131 regvalue = pregister->clkenb; in nx_disp_top_clkgen_set_clock_pclk_mode()
135 writel(regvalue, &pregister->clkenb); in nx_disp_top_clkgen_set_clock_pclk_mode()
218 read_value = pregister->clkenb; in nx_disp_top_clkgen_set_clock_divisor_enable()
222 writel(read_value, &pregister->clkenb); in nx_disp_top_clkgen_set_clock_divisor_enable()
233 return (int)((pregister->clkenb & in nx_disp_top_clkgen_get_clock_divisor_enable()
276 read_value = pregister->clkenb; in nx_disp_top_clkgen_set_input_inv()
280 writel(read_value, &pregister->clkenb); in nx_disp_top_clkgen_set_input_inv()
[all …]
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