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Searched refs:clock_cntl (Results 1 – 17 of 17) sorted by relevance

/dports/graphics/svgalib/svgalib-1.4.3/src/
H A Drage.c405 clock_cntl, bus_cntl, mem_vga_wp_sel, mem_vga_rp_sel, member
751 save->clock_cntl = inl(ATIIOPortCLOCK_CNTL); in rage_saveregs()
828 outl(ATIIOPortCLOCK_CNTL, restore->clock_cntl); in rage_setregs()
959 ATINewHWPtr->clock_cntl=ATIClockToProgram; in rage_initializemode()
/dports/graphics/svgalib/svgalib-1.4.3/mach/
H A Dmach64.c811 pcrtc->clock_cntl = 0x00 | 0x10; in mach64_crtc_programming()
813 pcrtc->clock_cntl = 0x08; in mach64_crtc_programming()
815 outb(CLOCK_CNTL, pcrtc->clock_cntl); in mach64_crtc_programming()
H A Dmach64.h450 UB clock_cntl; member
/dports/x11-drivers/xf86-video-mach64/xf86-video-mach64-6.9.6/src/
H A Datistruct.h128 clock_cntl, bus_cntl, mem_cntl, mem_vga_wp_sel, mem_vga_rp_sel, member
H A Daticlock.c290 pATIHW->clock_cntl = CLOCK_STROBE | in ATIClockCalculate()
H A Datimach64.c420 pATIHW->clock_cntl = inr(CLOCK_CNTL); in ATIMach64Save()
860 outr(CLOCK_CNTL, pATIHW->clock_cntl | CLOCK_STROBE); in ATIMach64Set()
/dports/multimedia/libv4l/linux-5.13-rc2/drivers/gpu/drm/amd/amdgpu/
H A Dcik.c1960 u32 clock_cntl, pc; in cik_need_reset_on_init() local
1966 clock_cntl = RREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0); in cik_need_reset_on_init()
1968 if ((0 == REG_GET_FIELD(clock_cntl, SMC_SYSCON_CLOCK_CNTL_0, ck_disable)) && in cik_need_reset_on_init()
H A Dvi.c1426 u32 clock_cntl, pc; in vi_need_reset_on_init() local
1432 clock_cntl = RREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0); in vi_need_reset_on_init()
1434 if ((0 == REG_GET_FIELD(clock_cntl, SMC_SYSCON_CLOCK_CNTL_0, ck_disable)) && in vi_need_reset_on_init()
/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/gpu/drm/amd/amdgpu/
H A Dcik.c1960 u32 clock_cntl, pc; in cik_need_reset_on_init() local
1966 clock_cntl = RREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0); in cik_need_reset_on_init()
1968 if ((0 == REG_GET_FIELD(clock_cntl, SMC_SYSCON_CLOCK_CNTL_0, ck_disable)) && in cik_need_reset_on_init()
H A Dvi.c1426 u32 clock_cntl, pc; in vi_need_reset_on_init() local
1432 clock_cntl = RREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0); in vi_need_reset_on_init()
1434 if ((0 == REG_GET_FIELD(clock_cntl, SMC_SYSCON_CLOCK_CNTL_0, ck_disable)) && in vi_need_reset_on_init()
/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/gpu/drm/amd/amdgpu/
H A Dcik.c1960 u32 clock_cntl, pc; in cik_need_reset_on_init() local
1966 clock_cntl = RREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0); in cik_need_reset_on_init()
1968 if ((0 == REG_GET_FIELD(clock_cntl, SMC_SYSCON_CLOCK_CNTL_0, ck_disable)) && in cik_need_reset_on_init()
H A Dvi.c1426 u32 clock_cntl, pc; in vi_need_reset_on_init() local
1432 clock_cntl = RREG32_SMC(ixSMC_SYSCON_CLOCK_CNTL_0); in vi_need_reset_on_init()
1434 if ((0 == REG_GET_FIELD(clock_cntl, SMC_SYSCON_CLOCK_CNTL_0, ck_disable)) && in vi_need_reset_on_init()
/dports/multimedia/libv4l/linux-5.13-rc2/drivers/video/fbdev/aty/
H A Datyfb_base.c3078 u8 clock_cntl; in atyfb_setup_sparc() local
3094 clock_cntl = aty_ld_8(CLOCK_CNTL, par); in atyfb_setup_sparc()
3107 N = pll_regs[VCLK0_FB_DIV + (clock_cntl & 3)]; in atyfb_setup_sparc()
3112 P = aty_postdividers[((pll_regs[VCLK_POST_DIV] >> ((clock_cntl & 3) << 1)) & 3) | in atyfb_setup_sparc()
3113 ((pll_regs[PLL_EXT_CNTL] >> (2 + (clock_cntl & 3))) & 4)]; in atyfb_setup_sparc()
/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/video/fbdev/aty/
H A Datyfb_base.c3078 u8 clock_cntl; in atyfb_setup_sparc() local
3094 clock_cntl = aty_ld_8(CLOCK_CNTL, par); in atyfb_setup_sparc()
3107 N = pll_regs[VCLK0_FB_DIV + (clock_cntl & 3)]; in atyfb_setup_sparc()
3112 P = aty_postdividers[((pll_regs[VCLK_POST_DIV] >> ((clock_cntl & 3) << 1)) & 3) | in atyfb_setup_sparc()
3113 ((pll_regs[PLL_EXT_CNTL] >> (2 + (clock_cntl & 3))) & 4)]; in atyfb_setup_sparc()
/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/video/fbdev/aty/
H A Datyfb_base.c3078 u8 clock_cntl; in atyfb_setup_sparc() local
3094 clock_cntl = aty_ld_8(CLOCK_CNTL, par); in atyfb_setup_sparc()
3107 N = pll_regs[VCLK0_FB_DIV + (clock_cntl & 3)]; in atyfb_setup_sparc()
3112 P = aty_postdividers[((pll_regs[VCLK_POST_DIV] >> ((clock_cntl & 3) << 1)) & 3) | in atyfb_setup_sparc()
3113 ((pll_regs[PLL_EXT_CNTL] >> (2 + (clock_cntl & 3))) & 4)]; in atyfb_setup_sparc()
/dports/emulators/pcem/pcem_emulator-pcem-faf5d6423060/src/
H A Dvid_ati_mach64.c95 uint32_t clock_cntl; member
1828 READ8(addr, mach64->clock_cntl); in mach64_ext_readb()
2307 WRITE8(addr, mach64->clock_cntl, val); in mach64_ext_writeb()
2313 mach64->ics2595.output_clock = mach64->pll_freq[mach64->clock_cntl & 3]; in mach64_ext_writeb()
/dports/misc/rump/buildrump.sh-b914579/src/sys/dev/pci/
H A Dmachfb.c155 uint32_t clock_cntl; member