| /dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp1/megacells/ |
| H A D | fifo_4k.v | 2315 clrn,
2320 input clrn; port
2450 clrn,
2455 input clrn; port
2577 clrn,
2582 input clrn; port
2591 .clrn(clrn),
3283 .clrn((~ aclr)),
3289 .clrn((~ aclr)),
3295 .clrn((~ aclr)),
[all …]
|
| H A D | fifo_2k.v | 2223 clrn,
2228 input clrn; port
2350 clrn,
2355 input clrn; port
2469 clrn,
2474 input clrn; port
2483 .clrn(clrn),
3131 .clrn((~ aclr)),
3137 .clrn((~ aclr)),
3143 .clrn((~ aclr)),
[all …]
|
| /dports/lang/slib/slib-3b6/ |
| H A D | grapheps.scm | 323 (define (set-color clrn)
325 (cond ((color? clrn) clrn)
326 ((number? clrn) (* 255/100 clrn))
327 ((or (eq? 'black clrn)
328 (and (string? clrn) (string-ci=? "black" clrn))) 0)
329 ((or (eq? 'white clrn)
330 (and (string? clrn) (string-ci=? "white" clrn))) 255)
331 (else (or (saturate clrn) (resene clrn)
332 (string->color (if (symbol? clrn)
333 (symbol->string clrn)
[all …]
|
| /dports/cad/yosys/yosys-yosys-0.12/techlibs/intel/common/ |
| H A D | ff_map.v | 5 …yg("TRUE"), .power_up("high")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R), .prn(1'b1), .en…
7 …wyg("TRUE"), .power_up("low")) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R), .prn(1'b1), .en…
|
| /dports/cad/yosys/yosys-yosys-0.12/techlibs/intel/cyclone10lp/ |
| H A D | cells_sim.v | 117 input d, clk, clrn, prn, ena, port
128 assign reset = (prn && sclr && ~clrn && ena);
|
| /dports/games/widelands/widelands-build21/src/graphic/text/ |
| H A D | rt_parse.cc | 59 uint32_t clrn = strtol(value_.c_str(), nullptr, 16); in get_color() local
60 return RGBColor((clrn >> 16) & 0xff, (clrn >> 8) & 0xff, clrn & 0xff); in get_color()
|
| /dports/cad/yosys/yosys-yosys-0.12/techlibs/intel_alm/cyclonev/ |
| H A D | cells_sim.v | 148 input d, clk, clrn, prn, ena, port
159 assign reset = (prn && sclr && ~clrn && ena);
|
| /dports/cad/yosys/yosys-yosys-0.12/techlibs/intel/cycloneiv/ |
| H A D | cells_sim.v | 118 input d, clk, clrn, prn, ena, port
129 assign reset = (prn && sclr && ~clrn && ena);
|
| /dports/cad/yosys/yosys-yosys-0.12/techlibs/intel/max10/ |
| H A D | cells_sim.v | 118 input d, clk, clrn, prn, ena, port
129 assign reset = (prn && sclr && ~clrn && ena);
|
| /dports/cad/yosys/yosys-yosys-0.12/techlibs/intel/cycloneive/ |
| H A D | cells_sim.v | 117 input d, clk, clrn, prn, ena, port
128 assign reset = (prn && sclr && ~clrn && ena);
|
| /dports/devel/binutils/binutils-2.37/gas/testsuite/gas/sparc/ |
| H A D | natural-32.s | 14 clrn [%g1]
|
| H A D | natural.s | 14 clrn [%g1]
|
| /dports/lang/gnatdroid-binutils-x86/binutils-2.27/gas/testsuite/gas/sparc/ |
| H A D | natural.s | 14 clrn [%g1]
|
| H A D | natural-32.s | 14 clrn [%g1]
|
| /dports/devel/arm-elf-binutils/binutils-2.37/gas/testsuite/gas/sparc/ |
| H A D | natural-32.s | 14 clrn [%g1]
|
| H A D | natural.s | 14 clrn [%g1]
|
| /dports/devel/gnulibiberty/binutils-2.37/gas/testsuite/gas/sparc/ |
| H A D | natural-32.s | 14 clrn [%g1]
|
| H A D | natural.s | 14 clrn [%g1]
|
| /dports/lang/gnatdroid-binutils/binutils-2.27/gas/testsuite/gas/sparc/ |
| H A D | natural-32.s | 14 clrn [%g1]
|
| H A D | natural.s | 14 clrn [%g1]
|
| /dports/devel/zpu-gcc/zpu-toolchain-1.0/toolchain/binutils/include/opcode/ |
| H A D | msp430.h | 62 MSP_INSN (clrn, 0, 0, 0xc222, 0xffff),
|
| /dports/devel/zpu-binutils/zpu-toolchain-1.0/toolchain/binutils/include/opcode/ |
| H A D | msp430.h | 62 MSP_INSN (clrn, 0, 0, 0xc222, 0xffff),
|
| /dports/devel/avr-gdb/gdb-7.3.1/include/opcode/ |
| H A D | msp430.h | 63 MSP_INSN (clrn, 0, 0, 0xc222, 0xffff),
|
| /dports/devel/gdb761/gdb-7.6.1/include/opcode/ |
| H A D | msp430.h | 63 MSP_INSN (clrn, 0, 0, 0xc222, 0xffff),
|
| /dports/devel/tigcc/tigcc-0.96.b8_10/gnu/binutils-2.16.1/include/opcode/ |
| H A D | msp430.h | 62 MSP_INSN (clrn, 0, 0, 0xc222, 0xffff),
|