/dports/cad/yosys/yosys-yosys-0.12/kernel/ |
H A D | macc.h | 111 log_assert(GetSize(config_bits) >= config_width); in from_cell() 114 if (config_bits[config_cursor++] == State::S1) num_bits |= 1; in from_cell() 130 if (config_bits[config_cursor++] == State::S1) in from_cell() 138 if (config_bits[config_cursor++] == State::S1) in from_cell() 155 std::vector<RTLIL::State> config_bits; in to_cell() local 167 config_bits.push_back(num_bits & 1 ? State::S1 : State::S0); in to_cell() 168 config_bits.push_back(num_bits & 2 ? State::S1 : State::S0); in to_cell() 169 config_bits.push_back(num_bits & 4 ? State::S1 : State::S0); in to_cell() 170 config_bits.push_back(num_bits & 8 ? State::S1 : State::S0); in to_cell() 194 cell->setParam(ID::CONFIG, config_bits); in to_cell() [all …]
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/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/comedi/drivers/ |
H A D | ni_at_a2150.c | 305 devpriv->config_bits &= ~CLOCK_MASK; in a2150_get_timing() 307 devpriv->config_bits |= in a2150_get_timing() 311 devpriv->config_bits |= in a2150_get_timing() 328 devpriv->config_bits &= ~CHANNEL_MASK; in a2150_set_chanlist() 489 devpriv->config_bits |= AC0_BIT; in a2150_ai_cmd() 491 devpriv->config_bits &= ~AC0_BIT; in a2150_ai_cmd() 493 devpriv->config_bits |= AC1_BIT; in a2150_ai_cmd() 495 devpriv->config_bits &= ~AC1_BIT; in a2150_ai_cmd() 593 devpriv->config_bits &= ~AC0_BIT; in a2150_ai_rinsn() 594 devpriv->config_bits &= ~AC1_BIT; in a2150_ai_rinsn() [all …]
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/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/comedi/drivers/ |
H A D | ni_at_a2150.c | 305 devpriv->config_bits &= ~CLOCK_MASK; in a2150_get_timing() 307 devpriv->config_bits |= in a2150_get_timing() 311 devpriv->config_bits |= in a2150_get_timing() 328 devpriv->config_bits &= ~CHANNEL_MASK; in a2150_set_chanlist() 489 devpriv->config_bits |= AC0_BIT; in a2150_ai_cmd() 491 devpriv->config_bits &= ~AC0_BIT; in a2150_ai_cmd() 493 devpriv->config_bits |= AC1_BIT; in a2150_ai_cmd() 495 devpriv->config_bits &= ~AC1_BIT; in a2150_ai_cmd() 593 devpriv->config_bits &= ~AC0_BIT; in a2150_ai_rinsn() 594 devpriv->config_bits &= ~AC1_BIT; in a2150_ai_rinsn() [all …]
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/dports/multimedia/libv4l/linux-5.13-rc2/drivers/comedi/drivers/ |
H A D | ni_at_a2150.c | 305 devpriv->config_bits &= ~CLOCK_MASK; in a2150_get_timing() 307 devpriv->config_bits |= in a2150_get_timing() 311 devpriv->config_bits |= in a2150_get_timing() 328 devpriv->config_bits &= ~CHANNEL_MASK; in a2150_set_chanlist() 489 devpriv->config_bits |= AC0_BIT; in a2150_ai_cmd() 491 devpriv->config_bits &= ~AC0_BIT; in a2150_ai_cmd() 493 devpriv->config_bits |= AC1_BIT; in a2150_ai_cmd() 495 devpriv->config_bits &= ~AC1_BIT; in a2150_ai_cmd() 593 devpriv->config_bits &= ~AC0_BIT; in a2150_ai_rinsn() 594 devpriv->config_bits &= ~AC1_BIT; in a2150_ai_rinsn() [all …]
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/dports/lang/clover/mesa-21.3.6/src/gallium/drivers/vc4/ |
H A D | vc4_emit.c | 106 (vc4->rasterizer->config_bits[0] | in vc4_emit_state() 107 vc4->zsa->config_bits[0]) & rasosm_mask_out); in vc4_emit_state() 109 vc4->rasterizer->config_bits[1] | in vc4_emit_state() 110 vc4->zsa->config_bits[1]); in vc4_emit_state() 112 (vc4->rasterizer->config_bits[2] | in vc4_emit_state() 113 vc4->zsa->config_bits[2]) & ez_enable_mask_out); in vc4_emit_state()
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H A D | vc4_state.c | 109 so->config_bits[0] |= VC4_CONFIG_BITS_ENABLE_PRIM_FRONT; in vc4_create_rasterizer_state() 111 so->config_bits[0] |= VC4_CONFIG_BITS_ENABLE_PRIM_BACK; in vc4_create_rasterizer_state() 121 so->config_bits[0] |= VC4_CONFIG_BITS_CW_PRIMITIVES; in vc4_create_rasterizer_state() 124 so->config_bits[0] |= VC4_CONFIG_BITS_ENABLE_DEPTH_OFFSET; in vc4_create_rasterizer_state() 133 so->config_bits[0] |= VC4_CONFIG_BITS_RASTERIZER_OVERSAMPLE_4X; in vc4_create_rasterizer_state() 221 so->config_bits[2] |= VC4_CONFIG_BITS_EARLY_Z_UPDATE; in vc4_create_depth_stencil_alpha_state() 225 so->config_bits[1] |= VC4_CONFIG_BITS_Z_UPDATE; in vc4_create_depth_stencil_alpha_state() 227 so->config_bits[1] |= (cso->depth_func << in vc4_create_depth_stencil_alpha_state() 240 so->config_bits[2] |= VC4_CONFIG_BITS_EARLY_Z; in vc4_create_depth_stencil_alpha_state() 243 so->config_bits[1] |= (PIPE_FUNC_ALWAYS << in vc4_create_depth_stencil_alpha_state()
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/dports/graphics/libosmesa/mesa-21.3.6/src/gallium/drivers/vc4/ |
H A D | vc4_emit.c | 106 (vc4->rasterizer->config_bits[0] | in vc4_emit_state() 107 vc4->zsa->config_bits[0]) & rasosm_mask_out); in vc4_emit_state() 109 vc4->rasterizer->config_bits[1] | in vc4_emit_state() 110 vc4->zsa->config_bits[1]); in vc4_emit_state() 112 (vc4->rasterizer->config_bits[2] | in vc4_emit_state() 113 vc4->zsa->config_bits[2]) & ez_enable_mask_out); in vc4_emit_state()
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H A D | vc4_state.c | 109 so->config_bits[0] |= VC4_CONFIG_BITS_ENABLE_PRIM_FRONT; in vc4_create_rasterizer_state() 111 so->config_bits[0] |= VC4_CONFIG_BITS_ENABLE_PRIM_BACK; in vc4_create_rasterizer_state() 121 so->config_bits[0] |= VC4_CONFIG_BITS_CW_PRIMITIVES; in vc4_create_rasterizer_state() 124 so->config_bits[0] |= VC4_CONFIG_BITS_ENABLE_DEPTH_OFFSET; in vc4_create_rasterizer_state() 133 so->config_bits[0] |= VC4_CONFIG_BITS_RASTERIZER_OVERSAMPLE_4X; in vc4_create_rasterizer_state() 221 so->config_bits[2] |= VC4_CONFIG_BITS_EARLY_Z_UPDATE; in vc4_create_depth_stencil_alpha_state() 225 so->config_bits[1] |= VC4_CONFIG_BITS_Z_UPDATE; in vc4_create_depth_stencil_alpha_state() 227 so->config_bits[1] |= (cso->depth_func << in vc4_create_depth_stencil_alpha_state() 240 so->config_bits[2] |= VC4_CONFIG_BITS_EARLY_Z; in vc4_create_depth_stencil_alpha_state() 243 so->config_bits[1] |= (PIPE_FUNC_ALWAYS << in vc4_create_depth_stencil_alpha_state()
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/dports/graphics/libosmesa-gallium/mesa-21.3.6/src/gallium/drivers/vc4/ |
H A D | vc4_emit.c | 106 (vc4->rasterizer->config_bits[0] | in vc4_emit_state() 107 vc4->zsa->config_bits[0]) & rasosm_mask_out); in vc4_emit_state() 109 vc4->rasterizer->config_bits[1] | in vc4_emit_state() 110 vc4->zsa->config_bits[1]); in vc4_emit_state() 112 (vc4->rasterizer->config_bits[2] | in vc4_emit_state() 113 vc4->zsa->config_bits[2]) & ez_enable_mask_out); in vc4_emit_state()
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H A D | vc4_state.c | 109 so->config_bits[0] |= VC4_CONFIG_BITS_ENABLE_PRIM_FRONT; in vc4_create_rasterizer_state() 111 so->config_bits[0] |= VC4_CONFIG_BITS_ENABLE_PRIM_BACK; in vc4_create_rasterizer_state() 121 so->config_bits[0] |= VC4_CONFIG_BITS_CW_PRIMITIVES; in vc4_create_rasterizer_state() 124 so->config_bits[0] |= VC4_CONFIG_BITS_ENABLE_DEPTH_OFFSET; in vc4_create_rasterizer_state() 133 so->config_bits[0] |= VC4_CONFIG_BITS_RASTERIZER_OVERSAMPLE_4X; in vc4_create_rasterizer_state() 221 so->config_bits[2] |= VC4_CONFIG_BITS_EARLY_Z_UPDATE; in vc4_create_depth_stencil_alpha_state() 225 so->config_bits[1] |= VC4_CONFIG_BITS_Z_UPDATE; in vc4_create_depth_stencil_alpha_state() 227 so->config_bits[1] |= (cso->depth_func << in vc4_create_depth_stencil_alpha_state() 240 so->config_bits[2] |= VC4_CONFIG_BITS_EARLY_Z; in vc4_create_depth_stencil_alpha_state() 243 so->config_bits[1] |= (PIPE_FUNC_ALWAYS << in vc4_create_depth_stencil_alpha_state()
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/dports/graphics/mesa-gallium-xa/mesa-21.3.6/src/gallium/drivers/vc4/ |
H A D | vc4_emit.c | 106 (vc4->rasterizer->config_bits[0] | in vc4_emit_state() 107 vc4->zsa->config_bits[0]) & rasosm_mask_out); in vc4_emit_state() 109 vc4->rasterizer->config_bits[1] | in vc4_emit_state() 110 vc4->zsa->config_bits[1]); in vc4_emit_state() 112 (vc4->rasterizer->config_bits[2] | in vc4_emit_state() 113 vc4->zsa->config_bits[2]) & ez_enable_mask_out); in vc4_emit_state()
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H A D | vc4_state.c | 109 so->config_bits[0] |= VC4_CONFIG_BITS_ENABLE_PRIM_FRONT; in vc4_create_rasterizer_state() 111 so->config_bits[0] |= VC4_CONFIG_BITS_ENABLE_PRIM_BACK; in vc4_create_rasterizer_state() 121 so->config_bits[0] |= VC4_CONFIG_BITS_CW_PRIMITIVES; in vc4_create_rasterizer_state() 124 so->config_bits[0] |= VC4_CONFIG_BITS_ENABLE_DEPTH_OFFSET; in vc4_create_rasterizer_state() 133 so->config_bits[0] |= VC4_CONFIG_BITS_RASTERIZER_OVERSAMPLE_4X; in vc4_create_rasterizer_state() 221 so->config_bits[2] |= VC4_CONFIG_BITS_EARLY_Z_UPDATE; in vc4_create_depth_stencil_alpha_state() 225 so->config_bits[1] |= VC4_CONFIG_BITS_Z_UPDATE; in vc4_create_depth_stencil_alpha_state() 227 so->config_bits[1] |= (cso->depth_func << in vc4_create_depth_stencil_alpha_state() 240 so->config_bits[2] |= VC4_CONFIG_BITS_EARLY_Z; in vc4_create_depth_stencil_alpha_state() 243 so->config_bits[1] |= (PIPE_FUNC_ALWAYS << in vc4_create_depth_stencil_alpha_state()
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/dports/graphics/mesa-libs/mesa-21.3.6/src/gallium/drivers/vc4/ |
H A D | vc4_emit.c | 106 (vc4->rasterizer->config_bits[0] | in vc4_emit_state() 107 vc4->zsa->config_bits[0]) & rasosm_mask_out); in vc4_emit_state() 109 vc4->rasterizer->config_bits[1] | in vc4_emit_state() 110 vc4->zsa->config_bits[1]); in vc4_emit_state() 112 (vc4->rasterizer->config_bits[2] | in vc4_emit_state() 113 vc4->zsa->config_bits[2]) & ez_enable_mask_out); in vc4_emit_state()
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H A D | vc4_state.c | 109 so->config_bits[0] |= VC4_CONFIG_BITS_ENABLE_PRIM_FRONT; in vc4_create_rasterizer_state() 111 so->config_bits[0] |= VC4_CONFIG_BITS_ENABLE_PRIM_BACK; in vc4_create_rasterizer_state() 121 so->config_bits[0] |= VC4_CONFIG_BITS_CW_PRIMITIVES; in vc4_create_rasterizer_state() 124 so->config_bits[0] |= VC4_CONFIG_BITS_ENABLE_DEPTH_OFFSET; in vc4_create_rasterizer_state() 133 so->config_bits[0] |= VC4_CONFIG_BITS_RASTERIZER_OVERSAMPLE_4X; in vc4_create_rasterizer_state() 221 so->config_bits[2] |= VC4_CONFIG_BITS_EARLY_Z_UPDATE; in vc4_create_depth_stencil_alpha_state() 225 so->config_bits[1] |= VC4_CONFIG_BITS_Z_UPDATE; in vc4_create_depth_stencil_alpha_state() 227 so->config_bits[1] |= (cso->depth_func << in vc4_create_depth_stencil_alpha_state() 240 so->config_bits[2] |= VC4_CONFIG_BITS_EARLY_Z; in vc4_create_depth_stencil_alpha_state() 243 so->config_bits[1] |= (PIPE_FUNC_ALWAYS << in vc4_create_depth_stencil_alpha_state()
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/dports/graphics/mesa-dri-gallium/mesa-21.3.6/src/gallium/drivers/vc4/ |
H A D | vc4_emit.c | 106 (vc4->rasterizer->config_bits[0] | in vc4_emit_state() 107 vc4->zsa->config_bits[0]) & rasosm_mask_out); in vc4_emit_state() 109 vc4->rasterizer->config_bits[1] | in vc4_emit_state() 110 vc4->zsa->config_bits[1]); in vc4_emit_state() 112 (vc4->rasterizer->config_bits[2] | in vc4_emit_state() 113 vc4->zsa->config_bits[2]) & ez_enable_mask_out); in vc4_emit_state()
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H A D | vc4_state.c | 109 so->config_bits[0] |= VC4_CONFIG_BITS_ENABLE_PRIM_FRONT; in vc4_create_rasterizer_state() 111 so->config_bits[0] |= VC4_CONFIG_BITS_ENABLE_PRIM_BACK; in vc4_create_rasterizer_state() 121 so->config_bits[0] |= VC4_CONFIG_BITS_CW_PRIMITIVES; in vc4_create_rasterizer_state() 124 so->config_bits[0] |= VC4_CONFIG_BITS_ENABLE_DEPTH_OFFSET; in vc4_create_rasterizer_state() 133 so->config_bits[0] |= VC4_CONFIG_BITS_RASTERIZER_OVERSAMPLE_4X; in vc4_create_rasterizer_state() 221 so->config_bits[2] |= VC4_CONFIG_BITS_EARLY_Z_UPDATE; in vc4_create_depth_stencil_alpha_state() 225 so->config_bits[1] |= VC4_CONFIG_BITS_Z_UPDATE; in vc4_create_depth_stencil_alpha_state() 227 so->config_bits[1] |= (cso->depth_func << in vc4_create_depth_stencil_alpha_state() 240 so->config_bits[2] |= VC4_CONFIG_BITS_EARLY_Z; in vc4_create_depth_stencil_alpha_state() 243 so->config_bits[1] |= (PIPE_FUNC_ALWAYS << in vc4_create_depth_stencil_alpha_state()
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/dports/graphics/mesa-gallium-va/mesa-21.3.6/src/gallium/drivers/vc4/ |
H A D | vc4_emit.c | 106 (vc4->rasterizer->config_bits[0] | in vc4_emit_state() 107 vc4->zsa->config_bits[0]) & rasosm_mask_out); in vc4_emit_state() 109 vc4->rasterizer->config_bits[1] | in vc4_emit_state() 110 vc4->zsa->config_bits[1]); in vc4_emit_state() 112 (vc4->rasterizer->config_bits[2] | in vc4_emit_state() 113 vc4->zsa->config_bits[2]) & ez_enable_mask_out); in vc4_emit_state()
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H A D | vc4_state.c | 109 so->config_bits[0] |= VC4_CONFIG_BITS_ENABLE_PRIM_FRONT; in vc4_create_rasterizer_state() 111 so->config_bits[0] |= VC4_CONFIG_BITS_ENABLE_PRIM_BACK; in vc4_create_rasterizer_state() 121 so->config_bits[0] |= VC4_CONFIG_BITS_CW_PRIMITIVES; in vc4_create_rasterizer_state() 124 so->config_bits[0] |= VC4_CONFIG_BITS_ENABLE_DEPTH_OFFSET; in vc4_create_rasterizer_state() 133 so->config_bits[0] |= VC4_CONFIG_BITS_RASTERIZER_OVERSAMPLE_4X; in vc4_create_rasterizer_state() 221 so->config_bits[2] |= VC4_CONFIG_BITS_EARLY_Z_UPDATE; in vc4_create_depth_stencil_alpha_state() 225 so->config_bits[1] |= VC4_CONFIG_BITS_Z_UPDATE; in vc4_create_depth_stencil_alpha_state() 227 so->config_bits[1] |= (cso->depth_func << in vc4_create_depth_stencil_alpha_state() 240 so->config_bits[2] |= VC4_CONFIG_BITS_EARLY_Z; in vc4_create_depth_stencil_alpha_state() 243 so->config_bits[1] |= (PIPE_FUNC_ALWAYS << in vc4_create_depth_stencil_alpha_state()
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/dports/graphics/mesa-gallium-vdpau/mesa-21.3.6/src/gallium/drivers/vc4/ |
H A D | vc4_emit.c | 106 (vc4->rasterizer->config_bits[0] | in vc4_emit_state() 107 vc4->zsa->config_bits[0]) & rasosm_mask_out); in vc4_emit_state() 109 vc4->rasterizer->config_bits[1] | in vc4_emit_state() 110 vc4->zsa->config_bits[1]); in vc4_emit_state() 112 (vc4->rasterizer->config_bits[2] | in vc4_emit_state() 113 vc4->zsa->config_bits[2]) & ez_enable_mask_out); in vc4_emit_state()
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H A D | vc4_state.c | 109 so->config_bits[0] |= VC4_CONFIG_BITS_ENABLE_PRIM_FRONT; in vc4_create_rasterizer_state() 111 so->config_bits[0] |= VC4_CONFIG_BITS_ENABLE_PRIM_BACK; in vc4_create_rasterizer_state() 121 so->config_bits[0] |= VC4_CONFIG_BITS_CW_PRIMITIVES; in vc4_create_rasterizer_state() 124 so->config_bits[0] |= VC4_CONFIG_BITS_ENABLE_DEPTH_OFFSET; in vc4_create_rasterizer_state() 133 so->config_bits[0] |= VC4_CONFIG_BITS_RASTERIZER_OVERSAMPLE_4X; in vc4_create_rasterizer_state() 221 so->config_bits[2] |= VC4_CONFIG_BITS_EARLY_Z_UPDATE; in vc4_create_depth_stencil_alpha_state() 225 so->config_bits[1] |= VC4_CONFIG_BITS_Z_UPDATE; in vc4_create_depth_stencil_alpha_state() 227 so->config_bits[1] |= (cso->depth_func << in vc4_create_depth_stencil_alpha_state() 240 so->config_bits[2] |= VC4_CONFIG_BITS_EARLY_Z; in vc4_create_depth_stencil_alpha_state() 243 so->config_bits[1] |= (PIPE_FUNC_ALWAYS << in vc4_create_depth_stencil_alpha_state()
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/dports/graphics/mesa-devel/mesa-22.0-branchpoint-2059-ge8a63cf61ec/src/gallium/drivers/vc4/ |
H A D | vc4_emit.c | 106 (vc4->rasterizer->config_bits[0] | in vc4_emit_state() 107 vc4->zsa->config_bits[0]) & rasosm_mask_out); in vc4_emit_state() 109 vc4->rasterizer->config_bits[1] | in vc4_emit_state() 110 vc4->zsa->config_bits[1]); in vc4_emit_state() 112 (vc4->rasterizer->config_bits[2] | in vc4_emit_state() 113 vc4->zsa->config_bits[2]) & ez_enable_mask_out); in vc4_emit_state()
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H A D | vc4_state.c | 109 so->config_bits[0] |= VC4_CONFIG_BITS_ENABLE_PRIM_FRONT; in vc4_create_rasterizer_state() 111 so->config_bits[0] |= VC4_CONFIG_BITS_ENABLE_PRIM_BACK; in vc4_create_rasterizer_state() 121 so->config_bits[0] |= VC4_CONFIG_BITS_CW_PRIMITIVES; in vc4_create_rasterizer_state() 124 so->config_bits[0] |= VC4_CONFIG_BITS_ENABLE_DEPTH_OFFSET; in vc4_create_rasterizer_state() 133 so->config_bits[0] |= VC4_CONFIG_BITS_RASTERIZER_OVERSAMPLE_4X; in vc4_create_rasterizer_state() 221 so->config_bits[2] |= VC4_CONFIG_BITS_EARLY_Z_UPDATE; in vc4_create_depth_stencil_alpha_state() 225 so->config_bits[1] |= VC4_CONFIG_BITS_Z_UPDATE; in vc4_create_depth_stencil_alpha_state() 227 so->config_bits[1] |= (cso->depth_func << in vc4_create_depth_stencil_alpha_state() 240 so->config_bits[2] |= VC4_CONFIG_BITS_EARLY_Z; in vc4_create_depth_stencil_alpha_state() 243 so->config_bits[1] |= (PIPE_FUNC_ALWAYS << in vc4_create_depth_stencil_alpha_state()
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/dports/graphics/mesa-dri-classic/mesa-20.2.3/src/gallium/drivers/vc4/ |
H A D | vc4_emit.c | 106 (vc4->rasterizer->config_bits[0] | in vc4_emit_state() 107 vc4->zsa->config_bits[0]) & rasosm_mask_out); in vc4_emit_state() 109 vc4->rasterizer->config_bits[1] | in vc4_emit_state() 110 vc4->zsa->config_bits[1]); in vc4_emit_state() 112 (vc4->rasterizer->config_bits[2] | in vc4_emit_state() 113 vc4->zsa->config_bits[2]) & ez_enable_mask_out); in vc4_emit_state()
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/dports/graphics/mesa-dri/mesa-21.3.6/src/gallium/drivers/vc4/ |
H A D | vc4_emit.c | 106 (vc4->rasterizer->config_bits[0] | in vc4_emit_state() 107 vc4->zsa->config_bits[0]) & rasosm_mask_out); in vc4_emit_state() 109 vc4->rasterizer->config_bits[1] | in vc4_emit_state() 110 vc4->zsa->config_bits[1]); in vc4_emit_state() 112 (vc4->rasterizer->config_bits[2] | in vc4_emit_state() 113 vc4->zsa->config_bits[2]) & ez_enable_mask_out); in vc4_emit_state()
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H A D | vc4_state.c | 109 so->config_bits[0] |= VC4_CONFIG_BITS_ENABLE_PRIM_FRONT; in vc4_create_rasterizer_state() 111 so->config_bits[0] |= VC4_CONFIG_BITS_ENABLE_PRIM_BACK; in vc4_create_rasterizer_state() 121 so->config_bits[0] |= VC4_CONFIG_BITS_CW_PRIMITIVES; in vc4_create_rasterizer_state() 124 so->config_bits[0] |= VC4_CONFIG_BITS_ENABLE_DEPTH_OFFSET; in vc4_create_rasterizer_state() 133 so->config_bits[0] |= VC4_CONFIG_BITS_RASTERIZER_OVERSAMPLE_4X; in vc4_create_rasterizer_state() 221 so->config_bits[2] |= VC4_CONFIG_BITS_EARLY_Z_UPDATE; in vc4_create_depth_stencil_alpha_state() 225 so->config_bits[1] |= VC4_CONFIG_BITS_Z_UPDATE; in vc4_create_depth_stencil_alpha_state() 227 so->config_bits[1] |= (cso->depth_func << in vc4_create_depth_stencil_alpha_state() 240 so->config_bits[2] |= VC4_CONFIG_BITS_EARLY_Z; in vc4_create_depth_stencil_alpha_state() 243 so->config_bits[1] |= (PIPE_FUNC_ALWAYS << in vc4_create_depth_stencil_alpha_state()
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