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Searched refs:control_phase (Results 1 – 20 of 20) sorted by relevance

/dports/misc/rump/buildrump.sh-b914579/src/sys/external/bsd/dwc2/dist/
H A Ddwc2_hcdddma.c712 qtd->control_phase == DWC2_CONTROL_SETUP) in dwc2_fill_host_dma_desc()
1110 if (qtd->control_phase == DWC2_CONTROL_DATA) { in dwc2_update_non_isoc_urb_state_ddma()
1120 } else if (qtd->control_phase == DWC2_CONTROL_STATUS) { in dwc2_update_non_isoc_urb_state_ddma()
1182 switch (qtd->control_phase) { in dwc2_process_non_isoc_desc()
1185 qtd->control_phase = DWC2_CONTROL_DATA; in dwc2_process_non_isoc_desc()
1187 qtd->control_phase = DWC2_CONTROL_STATUS; in dwc2_process_non_isoc_desc()
1193 qtd->control_phase = DWC2_CONTROL_STATUS; in dwc2_process_non_isoc_desc()
H A Ddwc2_hcdintr.c1046 switch (qtd->control_phase) { in dwc2_hc_xfercomp_intr()
1049 qtd->control_phase = DWC2_CONTROL_DATA; in dwc2_hc_xfercomp_intr()
1051 qtd->control_phase = DWC2_CONTROL_STATUS; in dwc2_hc_xfercomp_intr()
1060 qtd->control_phase = DWC2_CONTROL_STATUS; in dwc2_hc_xfercomp_intr()
H A Ddwc2_hcd.h350 enum dwc2_control_phase control_phase; member
H A Ddwc2_hcdqueue.c780 qtd->control_phase = DWC2_CONTROL_SETUP; in dwc2_hcd_qtd_init()
H A Ddwc2_hcd.c623 switch (qtd->control_phase) { in dwc2_hc_init_xfer()
/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/usb/dwc2/
H A Dhcd_ddma.c718 qtd->control_phase == DWC2_CONTROL_SETUP) in dwc2_fill_host_dma_desc()
1120 if (qtd->control_phase == DWC2_CONTROL_DATA) { in dwc2_update_non_isoc_urb_state_ddma()
1130 } else if (qtd->control_phase == DWC2_CONTROL_STATUS) { in dwc2_update_non_isoc_urb_state_ddma()
1190 switch (qtd->control_phase) { in dwc2_process_non_isoc_desc()
1193 qtd->control_phase = DWC2_CONTROL_DATA; in dwc2_process_non_isoc_desc()
1195 qtd->control_phase = DWC2_CONTROL_STATUS; in dwc2_process_non_isoc_desc()
1201 qtd->control_phase = DWC2_CONTROL_STATUS; in dwc2_process_non_isoc_desc()
H A Dhcd_intr.c1031 switch (qtd->control_phase) { in dwc2_hc_xfercomp_intr()
1034 qtd->control_phase = DWC2_CONTROL_DATA; in dwc2_hc_xfercomp_intr()
1036 qtd->control_phase = DWC2_CONTROL_STATUS; in dwc2_hc_xfercomp_intr()
1045 qtd->control_phase = DWC2_CONTROL_STATUS; in dwc2_hc_xfercomp_intr()
H A Dhcd.h432 enum dwc2_control_phase control_phase; member
H A Dhcd_queue.c2052 qtd->control_phase = DWC2_CONTROL_SETUP; in dwc2_hcd_qtd_init()
H A Dhcd.c2363 switch (qtd->control_phase) { in dwc2_hc_init_xfer()
/dports/multimedia/libv4l/linux-5.13-rc2/drivers/usb/dwc2/
H A Dhcd_ddma.c718 qtd->control_phase == DWC2_CONTROL_SETUP) in dwc2_fill_host_dma_desc()
1120 if (qtd->control_phase == DWC2_CONTROL_DATA) { in dwc2_update_non_isoc_urb_state_ddma()
1130 } else if (qtd->control_phase == DWC2_CONTROL_STATUS) { in dwc2_update_non_isoc_urb_state_ddma()
1190 switch (qtd->control_phase) { in dwc2_process_non_isoc_desc()
1193 qtd->control_phase = DWC2_CONTROL_DATA; in dwc2_process_non_isoc_desc()
1195 qtd->control_phase = DWC2_CONTROL_STATUS; in dwc2_process_non_isoc_desc()
1201 qtd->control_phase = DWC2_CONTROL_STATUS; in dwc2_process_non_isoc_desc()
H A Dhcd_intr.c1031 switch (qtd->control_phase) { in dwc2_hc_xfercomp_intr()
1034 qtd->control_phase = DWC2_CONTROL_DATA; in dwc2_hc_xfercomp_intr()
1036 qtd->control_phase = DWC2_CONTROL_STATUS; in dwc2_hc_xfercomp_intr()
1045 qtd->control_phase = DWC2_CONTROL_STATUS; in dwc2_hc_xfercomp_intr()
H A Dhcd.h432 enum dwc2_control_phase control_phase; member
H A Dhcd_queue.c2052 qtd->control_phase = DWC2_CONTROL_SETUP; in dwc2_hcd_qtd_init()
H A Dhcd.c2363 switch (qtd->control_phase) { in dwc2_hc_init_xfer()
/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/usb/dwc2/
H A Dhcd_ddma.c718 qtd->control_phase == DWC2_CONTROL_SETUP) in dwc2_fill_host_dma_desc()
1120 if (qtd->control_phase == DWC2_CONTROL_DATA) { in dwc2_update_non_isoc_urb_state_ddma()
1130 } else if (qtd->control_phase == DWC2_CONTROL_STATUS) { in dwc2_update_non_isoc_urb_state_ddma()
1190 switch (qtd->control_phase) { in dwc2_process_non_isoc_desc()
1193 qtd->control_phase = DWC2_CONTROL_DATA; in dwc2_process_non_isoc_desc()
1195 qtd->control_phase = DWC2_CONTROL_STATUS; in dwc2_process_non_isoc_desc()
1201 qtd->control_phase = DWC2_CONTROL_STATUS; in dwc2_process_non_isoc_desc()
H A Dhcd_intr.c1031 switch (qtd->control_phase) { in dwc2_hc_xfercomp_intr()
1034 qtd->control_phase = DWC2_CONTROL_DATA; in dwc2_hc_xfercomp_intr()
1036 qtd->control_phase = DWC2_CONTROL_STATUS; in dwc2_hc_xfercomp_intr()
1045 qtd->control_phase = DWC2_CONTROL_STATUS; in dwc2_hc_xfercomp_intr()
H A Dhcd.h432 enum dwc2_control_phase control_phase; member
H A Dhcd_queue.c2052 qtd->control_phase = DWC2_CONTROL_SETUP; in dwc2_hcd_qtd_init()
H A Dhcd.c2363 switch (qtd->control_phase) { in dwc2_hc_init_xfer()