/dports/emulators/qemu-utils/qemu-4.2.1/target/microblaze/ |
H A D | translate.c | 58 static TCGv_i64 cpu_SR[14]; variable 126 tcg_gen_movi_i64(cpu_SR[SR_PC], dc->pc); in t_gen_raise_exception() 145 tcg_gen_movi_i64(cpu_SR[SR_PC], dest); in gen_goto_tb() 148 tcg_gen_movi_i64(cpu_SR[SR_PC], dest); in gen_goto_tb() 155 tcg_gen_extrl_i64_i32(d, cpu_SR[SR_MSR]); in read_carry() 168 tcg_gen_deposit_i64(cpu_SR[SR_MSR], cpu_SR[SR_MSR], t0, 2, 1); in write_carry() 169 tcg_gen_deposit_i64(cpu_SR[SR_MSR], cpu_SR[SR_MSR], t0, 31, 1); in write_carry() 440 tcg_gen_extrl_i64_i32(d, cpu_SR[SR_MSR]); in msr_read() 452 tcg_gen_andi_i64(cpu_SR[SR_MSR], cpu_SR[SR_MSR], MSR_PVR); in msr_write() 453 tcg_gen_or_i64(cpu_SR[SR_MSR], cpu_SR[SR_MSR], t); in msr_write() [all …]
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/dports/emulators/qemu-guest-agent/qemu-5.0.1/target/microblaze/ |
H A D | translate.c | 58 static TCGv_i64 cpu_SR[14]; variable 126 tcg_gen_movi_i64(cpu_SR[SR_PC], dc->pc); in t_gen_raise_exception() 145 tcg_gen_movi_i64(cpu_SR[SR_PC], dest); in gen_goto_tb() 148 tcg_gen_movi_i64(cpu_SR[SR_PC], dest); in gen_goto_tb() 155 tcg_gen_extrl_i64_i32(d, cpu_SR[SR_MSR]); in read_carry() 168 tcg_gen_deposit_i64(cpu_SR[SR_MSR], cpu_SR[SR_MSR], t0, 2, 1); in write_carry() 169 tcg_gen_deposit_i64(cpu_SR[SR_MSR], cpu_SR[SR_MSR], t0, 31, 1); in write_carry() 440 tcg_gen_extrl_i64_i32(d, cpu_SR[SR_MSR]); in msr_read() 452 tcg_gen_andi_i64(cpu_SR[SR_MSR], cpu_SR[SR_MSR], MSR_PVR); in msr_write() 453 tcg_gen_or_i64(cpu_SR[SR_MSR], cpu_SR[SR_MSR], t); in msr_write() [all …]
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/dports/emulators/qemu42/qemu-4.2.1/target/microblaze/ |
H A D | translate.c | 58 static TCGv_i64 cpu_SR[14]; variable 126 tcg_gen_movi_i64(cpu_SR[SR_PC], dc->pc); in t_gen_raise_exception() 145 tcg_gen_movi_i64(cpu_SR[SR_PC], dest); in gen_goto_tb() 148 tcg_gen_movi_i64(cpu_SR[SR_PC], dest); in gen_goto_tb() 155 tcg_gen_extrl_i64_i32(d, cpu_SR[SR_MSR]); in read_carry() 168 tcg_gen_deposit_i64(cpu_SR[SR_MSR], cpu_SR[SR_MSR], t0, 2, 1); in write_carry() 169 tcg_gen_deposit_i64(cpu_SR[SR_MSR], cpu_SR[SR_MSR], t0, 31, 1); in write_carry() 440 tcg_gen_extrl_i64_i32(d, cpu_SR[SR_MSR]); in msr_read() 452 tcg_gen_andi_i64(cpu_SR[SR_MSR], cpu_SR[SR_MSR], MSR_PVR); in msr_write() 453 tcg_gen_or_i64(cpu_SR[SR_MSR], cpu_SR[SR_MSR], t); in msr_write() [all …]
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/dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/target/microblaze/ |
H A D | translate.c | 58 static TCGv_i64 cpu_SR[14]; variable 126 tcg_gen_movi_i64(cpu_SR[SR_PC], dc->pc); in t_gen_raise_exception() 145 tcg_gen_movi_i64(cpu_SR[SR_PC], dest); in gen_goto_tb() 148 tcg_gen_movi_i64(cpu_SR[SR_PC], dest); in gen_goto_tb() 155 tcg_gen_extrl_i64_i32(d, cpu_SR[SR_MSR]); in read_carry() 168 tcg_gen_deposit_i64(cpu_SR[SR_MSR], cpu_SR[SR_MSR], t0, 2, 1); in write_carry() 169 tcg_gen_deposit_i64(cpu_SR[SR_MSR], cpu_SR[SR_MSR], t0, 31, 1); in write_carry() 440 tcg_gen_extrl_i64_i32(d, cpu_SR[SR_MSR]); in msr_read() 452 tcg_gen_andi_i64(cpu_SR[SR_MSR], cpu_SR[SR_MSR], MSR_PVR); in msr_write() 453 tcg_gen_or_i64(cpu_SR[SR_MSR], cpu_SR[SR_MSR], t); in msr_write() [all …]
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/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/target/microblaze/ |
H A D | translate.c | 57 static TCGv_i64 cpu_SR[14]; variable 125 tcg_gen_movi_i64(cpu_SR[SR_PC], dc->pc); in t_gen_raise_exception() 144 tcg_gen_movi_i64(cpu_SR[SR_PC], dest); in gen_goto_tb() 147 tcg_gen_movi_i64(cpu_SR[SR_PC], dest); in gen_goto_tb() 154 tcg_gen_extrl_i64_i32(d, cpu_SR[SR_MSR]); in read_carry() 167 tcg_gen_deposit_i64(cpu_SR[SR_MSR], cpu_SR[SR_MSR], t0, 2, 1); in write_carry() 168 tcg_gen_deposit_i64(cpu_SR[SR_MSR], cpu_SR[SR_MSR], t0, 31, 1); in write_carry() 439 tcg_gen_extrl_i64_i32(d, cpu_SR[SR_MSR]); in msr_read() 451 tcg_gen_andi_i64(cpu_SR[SR_MSR], cpu_SR[SR_MSR], MSR_PVR); in msr_write() 452 tcg_gen_or_i64(cpu_SR[SR_MSR], cpu_SR[SR_MSR], t); in msr_write() [all …]
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/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/target/xtensa/ |
H A D | translate.c | 407 tcg_gen_deposit_i32(cpu_SR[PS], cpu_SR[PS], in gen_callw_slot() 440 tcg_gen_subi_i32(cpu_SR[LCOUNT], cpu_SR[LCOUNT], 1); in gen_check_loop_end() 673 tcg_gen_andc_i32(cpu_SR[INTSET], cpu_SR[INTSET], tmp); in gen_wsr_intclear() 726 tcg_gen_andi_i32(cpu_SR[INTSET], cpu_SR[INTSET], ~int_bit); in gen_wsr_ccompare() 1377 tcg_gen_deposit_i32(cpu_SR[BR], cpu_SR[BR], in translate_all() 1809 tcg_gen_ext8s_i32(cpu_SR[ACCHI], cpu_SR[ACCHI]); in translate_mac16() 2066 tcg_gen_andi_i32(cpu_SR[PS], cpu_SR[PS], ~PS_EXCM); in translate_rfe() 2073 tcg_gen_mov_i32(cpu_SR[PS], cpu_SR[EPS2 + arg[0] - 2]); in translate_rfi() 2082 tcg_gen_andi_i32(cpu_SR[PS], cpu_SR[PS], ~PS_EXCM); in translate_rfw() 2110 tcg_gen_andi_i32(cpu_SR[PS], cpu_SR[PS], ~PS_INTLEVEL); in translate_rsil() [all …]
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/dports/emulators/qemu-utils/qemu-4.2.1/target/xtensa/ |
H A D | translate.c | 409 tcg_gen_deposit_i32(cpu_SR[PS], cpu_SR[PS], in gen_callw_slot() 423 tcg_gen_subi_i32(cpu_SR[LCOUNT], cpu_SR[LCOUNT], 1); in gen_check_loop_end() 1875 tcg_gen_add2_i32(cpu_SR[ACCLO], cpu_SR[ACCHI], in translate_mac16() 1876 cpu_SR[ACCLO], cpu_SR[ACCHI], in translate_mac16() 1879 tcg_gen_sub2_i32(cpu_SR[ACCLO], cpu_SR[ACCHI], in translate_mac16() 1880 cpu_SR[ACCLO], cpu_SR[ACCHI], in translate_mac16() 1883 tcg_gen_ext8s_i32(cpu_SR[ACCHI], cpu_SR[ACCHI]); in translate_mac16() 2154 tcg_gen_andi_i32(cpu_SR[PS], cpu_SR[PS], ~PS_EXCM); in translate_rfe() 2170 tcg_gen_andi_i32(cpu_SR[PS], cpu_SR[PS], ~PS_EXCM); in translate_rfw() 2196 tcg_gen_andi_i32(cpu_SR[PS], cpu_SR[PS], ~PS_INTLEVEL); in translate_rsil() [all …]
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/dports/emulators/qemu-guest-agent/qemu-5.0.1/target/xtensa/ |
H A D | translate.c | 409 tcg_gen_deposit_i32(cpu_SR[PS], cpu_SR[PS], in gen_callw_slot() 423 tcg_gen_subi_i32(cpu_SR[LCOUNT], cpu_SR[LCOUNT], 1); in gen_check_loop_end() 1866 tcg_gen_add2_i32(cpu_SR[ACCLO], cpu_SR[ACCHI], in translate_mac16() 1867 cpu_SR[ACCLO], cpu_SR[ACCHI], in translate_mac16() 1870 tcg_gen_sub2_i32(cpu_SR[ACCLO], cpu_SR[ACCHI], in translate_mac16() 1871 cpu_SR[ACCLO], cpu_SR[ACCHI], in translate_mac16() 1874 tcg_gen_ext8s_i32(cpu_SR[ACCHI], cpu_SR[ACCHI]); in translate_mac16() 2145 tcg_gen_andi_i32(cpu_SR[PS], cpu_SR[PS], ~PS_EXCM); in translate_rfe() 2161 tcg_gen_andi_i32(cpu_SR[PS], cpu_SR[PS], ~PS_EXCM); in translate_rfw() 2187 tcg_gen_andi_i32(cpu_SR[PS], cpu_SR[PS], ~PS_INTLEVEL); in translate_rsil() [all …]
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/dports/emulators/qemu42/qemu-4.2.1/target/xtensa/ |
H A D | translate.c | 409 tcg_gen_deposit_i32(cpu_SR[PS], cpu_SR[PS], in gen_callw_slot() 423 tcg_gen_subi_i32(cpu_SR[LCOUNT], cpu_SR[LCOUNT], 1); in gen_check_loop_end() 1875 tcg_gen_add2_i32(cpu_SR[ACCLO], cpu_SR[ACCHI], in translate_mac16() 1876 cpu_SR[ACCLO], cpu_SR[ACCHI], in translate_mac16() 1879 tcg_gen_sub2_i32(cpu_SR[ACCLO], cpu_SR[ACCHI], in translate_mac16() 1880 cpu_SR[ACCLO], cpu_SR[ACCHI], in translate_mac16() 1883 tcg_gen_ext8s_i32(cpu_SR[ACCHI], cpu_SR[ACCHI]); in translate_mac16() 2154 tcg_gen_andi_i32(cpu_SR[PS], cpu_SR[PS], ~PS_EXCM); in translate_rfe() 2170 tcg_gen_andi_i32(cpu_SR[PS], cpu_SR[PS], ~PS_EXCM); in translate_rfw() 2196 tcg_gen_andi_i32(cpu_SR[PS], cpu_SR[PS], ~PS_INTLEVEL); in translate_rsil() [all …]
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/dports/emulators/qemu-cheri/qemu-0a323821042c36e21ea80e58b9545dfc3b0cb8ef/target/xtensa/ |
H A D | translate.c | 409 tcg_gen_deposit_i32(cpu_SR[PS], cpu_SR[PS], in gen_callw_slot() 423 tcg_gen_subi_i32(cpu_SR[LCOUNT], cpu_SR[LCOUNT], 1); in gen_check_loop_end() 1875 tcg_gen_add2_i32(cpu_SR[ACCLO], cpu_SR[ACCHI], in translate_mac16() 1876 cpu_SR[ACCLO], cpu_SR[ACCHI], in translate_mac16() 1879 tcg_gen_sub2_i32(cpu_SR[ACCLO], cpu_SR[ACCHI], in translate_mac16() 1880 cpu_SR[ACCLO], cpu_SR[ACCHI], in translate_mac16() 1883 tcg_gen_ext8s_i32(cpu_SR[ACCHI], cpu_SR[ACCHI]); in translate_mac16() 2154 tcg_gen_andi_i32(cpu_SR[PS], cpu_SR[PS], ~PS_EXCM); in translate_rfe() 2170 tcg_gen_andi_i32(cpu_SR[PS], cpu_SR[PS], ~PS_EXCM); in translate_rfw() 2196 tcg_gen_andi_i32(cpu_SR[PS], cpu_SR[PS], ~PS_INTLEVEL); in translate_rsil() [all …]
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/dports/emulators/qemu5/qemu-5.2.0/target/xtensa/ |
H A D | translate.c | 438 tcg_gen_deposit_i32(cpu_SR[PS], cpu_SR[PS], in gen_callw_slot() 452 tcg_gen_subi_i32(cpu_SR[LCOUNT], cpu_SR[LCOUNT], 1); in gen_check_loop_end() 1936 tcg_gen_add2_i32(cpu_SR[ACCLO], cpu_SR[ACCHI], in translate_mac16() 1937 cpu_SR[ACCLO], cpu_SR[ACCHI], in translate_mac16() 1940 tcg_gen_sub2_i32(cpu_SR[ACCLO], cpu_SR[ACCHI], in translate_mac16() 1941 cpu_SR[ACCLO], cpu_SR[ACCHI], in translate_mac16() 1944 tcg_gen_ext8s_i32(cpu_SR[ACCHI], cpu_SR[ACCHI]); in translate_mac16() 2215 tcg_gen_andi_i32(cpu_SR[PS], cpu_SR[PS], ~PS_EXCM); in translate_rfe() 2231 tcg_gen_andi_i32(cpu_SR[PS], cpu_SR[PS], ~PS_EXCM); in translate_rfw() 2257 tcg_gen_andi_i32(cpu_SR[PS], cpu_SR[PS], ~PS_INTLEVEL); in translate_rsil() [all …]
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/dports/emulators/qemu-devel/qemu-de8ed1055c2ce18c95f597eb10df360dcb534f99/target/xtensa/ |
H A D | translate.c | 423 tcg_gen_deposit_i32(cpu_SR[PS], cpu_SR[PS], in gen_callw_slot() 437 tcg_gen_subi_i32(cpu_SR[LCOUNT], cpu_SR[LCOUNT], 1); in gen_check_loop_end() 1905 tcg_gen_add2_i32(cpu_SR[ACCLO], cpu_SR[ACCHI], in translate_mac16() 1906 cpu_SR[ACCLO], cpu_SR[ACCHI], in translate_mac16() 1909 tcg_gen_sub2_i32(cpu_SR[ACCLO], cpu_SR[ACCHI], in translate_mac16() 1910 cpu_SR[ACCLO], cpu_SR[ACCHI], in translate_mac16() 1913 tcg_gen_ext8s_i32(cpu_SR[ACCHI], cpu_SR[ACCHI]); in translate_mac16() 2184 tcg_gen_andi_i32(cpu_SR[PS], cpu_SR[PS], ~PS_EXCM); in translate_rfe() 2200 tcg_gen_andi_i32(cpu_SR[PS], cpu_SR[PS], ~PS_EXCM); in translate_rfw() 2226 tcg_gen_andi_i32(cpu_SR[PS], cpu_SR[PS], ~PS_INTLEVEL); in translate_rsil() [all …]
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/dports/emulators/qemu/qemu-6.2.0/target/xtensa/ |
H A D | translate.c | 419 tcg_gen_deposit_i32(cpu_SR[PS], cpu_SR[PS], in gen_callw_slot() 433 tcg_gen_subi_i32(cpu_SR[LCOUNT], cpu_SR[LCOUNT], 1); in gen_check_loop_end() 1896 tcg_gen_add2_i32(cpu_SR[ACCLO], cpu_SR[ACCHI], in translate_mac16() 1897 cpu_SR[ACCLO], cpu_SR[ACCHI], in translate_mac16() 1900 tcg_gen_sub2_i32(cpu_SR[ACCLO], cpu_SR[ACCHI], in translate_mac16() 1901 cpu_SR[ACCLO], cpu_SR[ACCHI], in translate_mac16() 1904 tcg_gen_ext8s_i32(cpu_SR[ACCHI], cpu_SR[ACCHI]); in translate_mac16() 2175 tcg_gen_andi_i32(cpu_SR[PS], cpu_SR[PS], ~PS_EXCM); in translate_rfe() 2191 tcg_gen_andi_i32(cpu_SR[PS], cpu_SR[PS], ~PS_EXCM); in translate_rfw() 2217 tcg_gen_andi_i32(cpu_SR[PS], cpu_SR[PS], ~PS_INTLEVEL); in translate_rsil() [all …]
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/dports/emulators/qemu60/qemu-6.0.0/target/xtensa/ |
H A D | translate.c | 438 tcg_gen_deposit_i32(cpu_SR[PS], cpu_SR[PS], in gen_callw_slot() 452 tcg_gen_subi_i32(cpu_SR[LCOUNT], cpu_SR[LCOUNT], 1); in gen_check_loop_end() 1936 tcg_gen_add2_i32(cpu_SR[ACCLO], cpu_SR[ACCHI], in translate_mac16() 1937 cpu_SR[ACCLO], cpu_SR[ACCHI], in translate_mac16() 1940 tcg_gen_sub2_i32(cpu_SR[ACCLO], cpu_SR[ACCHI], in translate_mac16() 1941 cpu_SR[ACCLO], cpu_SR[ACCHI], in translate_mac16() 1944 tcg_gen_ext8s_i32(cpu_SR[ACCHI], cpu_SR[ACCHI]); in translate_mac16() 2215 tcg_gen_andi_i32(cpu_SR[PS], cpu_SR[PS], ~PS_EXCM); in translate_rfe() 2231 tcg_gen_andi_i32(cpu_SR[PS], cpu_SR[PS], ~PS_EXCM); in translate_rfw() 2257 tcg_gen_andi_i32(cpu_SR[PS], cpu_SR[PS], ~PS_INTLEVEL); in translate_rsil() [all …]
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