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/dports/emulators/pcem/pcem_emulator-pcem-faf5d6423060/src/
H A Dx86_ops_mmx_arith.h145 cpu_state.MM[cpu_reg].b[0] = USATB(cpu_state.MM[cpu_reg].b[0] + src.b[0]); in opPADDUSB_a16()
146 cpu_state.MM[cpu_reg].b[1] = USATB(cpu_state.MM[cpu_reg].b[1] + src.b[1]); in opPADDUSB_a16()
147 cpu_state.MM[cpu_reg].b[2] = USATB(cpu_state.MM[cpu_reg].b[2] + src.b[2]); in opPADDUSB_a16()
148 cpu_state.MM[cpu_reg].b[3] = USATB(cpu_state.MM[cpu_reg].b[3] + src.b[3]); in opPADDUSB_a16()
149 cpu_state.MM[cpu_reg].b[4] = USATB(cpu_state.MM[cpu_reg].b[4] + src.b[4]); in opPADDUSB_a16()
150 cpu_state.MM[cpu_reg].b[5] = USATB(cpu_state.MM[cpu_reg].b[5] + src.b[5]); in opPADDUSB_a16()
151 cpu_state.MM[cpu_reg].b[6] = USATB(cpu_state.MM[cpu_reg].b[6] + src.b[6]); in opPADDUSB_a16()
152 cpu_state.MM[cpu_reg].b[7] = USATB(cpu_state.MM[cpu_reg].b[7] + src.b[7]); in opPADDUSB_a16()
164 cpu_state.MM[cpu_reg].b[0] = USATB(cpu_state.MM[cpu_reg].b[0] + src.b[0]); in opPADDUSB_a32()
165 cpu_state.MM[cpu_reg].b[1] = USATB(cpu_state.MM[cpu_reg].b[1] + src.b[1]); in opPADDUSB_a32()
[all …]
H A Dx86_ops_mmx_cmp.h10 cpu_state.MM[cpu_reg].b[0] = (cpu_state.MM[cpu_reg].b[0] == src.b[0]) ? 0xff : 0; in opPCMPEQB_a16()
11 cpu_state.MM[cpu_reg].b[1] = (cpu_state.MM[cpu_reg].b[1] == src.b[1]) ? 0xff : 0; in opPCMPEQB_a16()
12 cpu_state.MM[cpu_reg].b[2] = (cpu_state.MM[cpu_reg].b[2] == src.b[2]) ? 0xff : 0; in opPCMPEQB_a16()
13 cpu_state.MM[cpu_reg].b[3] = (cpu_state.MM[cpu_reg].b[3] == src.b[3]) ? 0xff : 0; in opPCMPEQB_a16()
14 cpu_state.MM[cpu_reg].b[4] = (cpu_state.MM[cpu_reg].b[4] == src.b[4]) ? 0xff : 0; in opPCMPEQB_a16()
15 cpu_state.MM[cpu_reg].b[5] = (cpu_state.MM[cpu_reg].b[5] == src.b[5]) ? 0xff : 0; in opPCMPEQB_a16()
16 cpu_state.MM[cpu_reg].b[6] = (cpu_state.MM[cpu_reg].b[6] == src.b[6]) ? 0xff : 0; in opPCMPEQB_a16()
17 cpu_state.MM[cpu_reg].b[7] = (cpu_state.MM[cpu_reg].b[7] == src.b[7]) ? 0xff : 0; in opPCMPEQB_a16()
30 cpu_state.MM[cpu_reg].b[0] = (cpu_state.MM[cpu_reg].b[0] == src.b[0]) ? 0xff : 0; in opPCMPEQB_a32()
31 cpu_state.MM[cpu_reg].b[1] = (cpu_state.MM[cpu_reg].b[1] == src.b[1]) ? 0xff : 0; in opPCMPEQB_a32()
[all …]
H A Dx86_ops_mmx_pack.h52 cpu_state.MM[cpu_reg].l[0] = cpu_state.MM[cpu_reg].l[1]; in opPUNPCKHDQ_a16()
65 cpu_state.MM[cpu_reg].l[0] = cpu_state.MM[cpu_reg].l[1]; in opPUNPCKHDQ_a32()
80 cpu_state.MM[cpu_reg].b[6] = cpu_state.MM[cpu_reg].b[3]; in opPUNPCKLBW_a16()
82 cpu_state.MM[cpu_reg].b[4] = cpu_state.MM[cpu_reg].b[2]; in opPUNPCKLBW_a16()
84 cpu_state.MM[cpu_reg].b[2] = cpu_state.MM[cpu_reg].b[1]; in opPUNPCKLBW_a16()
86 cpu_state.MM[cpu_reg].b[0] = cpu_state.MM[cpu_reg].b[0]; in opPUNPCKLBW_a16()
99 cpu_state.MM[cpu_reg].b[6] = cpu_state.MM[cpu_reg].b[3]; in opPUNPCKLBW_a32()
101 cpu_state.MM[cpu_reg].b[4] = cpu_state.MM[cpu_reg].b[2]; in opPUNPCKLBW_a32()
103 cpu_state.MM[cpu_reg].b[2] = cpu_state.MM[cpu_reg].b[1]; in opPUNPCKLBW_a32()
105 cpu_state.MM[cpu_reg].b[0] = cpu_state.MM[cpu_reg].b[0]; in opPUNPCKLBW_a32()
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H A Dx86_ops_mmx_shift.h75 cpu_state.MM[cpu_reg].q = 0; in opPSLLW_a16()
96 cpu_state.MM[cpu_reg].q = 0; in opPSLLW_a32()
118 cpu_state.MM[cpu_reg].q = 0; in opPSRLW_a16()
139 cpu_state.MM[cpu_reg].q = 0; in opPSRLW_a32()
246 cpu_state.MM[cpu_reg].q = 0; in opPSLLD_a16()
265 cpu_state.MM[cpu_reg].q = 0; in opPSLLD_a32()
285 cpu_state.MM[cpu_reg].q = 0; in opPSRLD_a16()
304 cpu_state.MM[cpu_reg].q = 0; in opPSRLD_a32()
398 cpu_state.MM[cpu_reg].q = 0; in opPSLLQ_a16()
414 cpu_state.MM[cpu_reg].q = 0; in opPSLLQ_a32()
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H A Dx86_ops_mmx_mov.h8 cpu_state.MM[cpu_reg].l[0] = cpu_state.regs[cpu_rm].l; in opMOVD_l_mm_a16()
9 cpu_state.MM[cpu_reg].l[1] = 0; in opMOVD_l_mm_a16()
17 cpu_state.MM[cpu_reg].l[0] = dst; in opMOVD_l_mm_a16()
18 cpu_state.MM[cpu_reg].l[1] = 0; in opMOVD_l_mm_a16()
32 cpu_state.MM[cpu_reg].l[1] = 0; in opMOVD_l_mm_a32()
40 cpu_state.MM[cpu_reg].l[0] = dst; in opMOVD_l_mm_a32()
41 cpu_state.MM[cpu_reg].l[1] = 0; in opMOVD_l_mm_a32()
92 cpu_state.MM[cpu_reg].q = cpu_state.MM[cpu_rm].q; in opMOVQ_q_mm_a16()
100 cpu_state.MM[cpu_reg].q = dst; in opMOVQ_q_mm_a16()
112 cpu_state.MM[cpu_reg].q = cpu_state.MM[cpu_rm].q; in opMOVQ_q_mm_a32()
[all …]
H A Dx86_ops_movx.h7 cpu_state.regs[cpu_reg].w = (uint16_t)temp; in opMOVZX_w_b_a16()
19 cpu_state.regs[cpu_reg].w = (uint16_t)temp; in opMOVZX_w_b_a32()
31 cpu_state.regs[cpu_reg].l = (uint32_t)temp; in opMOVZX_l_b_a16()
43 cpu_state.regs[cpu_reg].l = (uint32_t)temp; in opMOVZX_l_b_a32()
55 cpu_state.regs[cpu_reg].w = temp; in opMOVZX_w_w_a16()
67 cpu_state.regs[cpu_reg].w = temp; in opMOVZX_w_w_a32()
79 cpu_state.regs[cpu_reg].l = (uint32_t)temp; in opMOVZX_l_w_a16()
91 cpu_state.regs[cpu_reg].l = (uint32_t)temp; in opMOVZX_l_w_a32()
104 cpu_state.regs[cpu_reg].w = (uint16_t)temp; in opMOVSX_w_b_a16()
118 cpu_state.regs[cpu_reg].w = (uint16_t)temp; in opMOVSX_w_b_a32()
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H A Dx86_ops_atomic.h12 if (AL == temp) seteab(getr8(cpu_reg)); in opCMPXCHG_b_a16()
30 if (AL == temp) seteab(getr8(cpu_reg)); in opCMPXCHG_b_a32()
187 setadd8(temp, getr8(cpu_reg)); in opXADD_b_a16()
188 setr8(cpu_reg, temp); in opXADD_b_a16()
204 setadd8(temp, getr8(cpu_reg)); in opXADD_b_a32()
205 setr8(cpu_reg, temp); in opXADD_b_a32()
222 setadd16(temp, cpu_state.regs[cpu_reg].w); in opXADD_w_a16()
223 cpu_state.regs[cpu_reg].w = temp; in opXADD_w_a16()
240 cpu_state.regs[cpu_reg].w = temp; in opXADD_w_a32()
258 cpu_state.regs[cpu_reg].l = temp; in opXADD_l_a16()
[all …]
H A Dx86_ops_mmx_logic.h9 cpu_state.MM[cpu_reg].q &= src.q; in opPAND_a16()
20 cpu_state.MM[cpu_reg].q &= src.q; in opPAND_a32()
32 cpu_state.MM[cpu_reg].q = ~cpu_state.MM[cpu_reg].q & src.q; in opPANDN_a16()
43 cpu_state.MM[cpu_reg].q = ~cpu_state.MM[cpu_reg].q & src.q; in opPANDN_a32()
55 cpu_state.MM[cpu_reg].q |= src.q; in opPOR_a16()
66 cpu_state.MM[cpu_reg].q |= src.q; in opPOR_a32()
78 cpu_state.MM[cpu_reg].q ^= src.q; in opPXOR_a16()
89 cpu_state.MM[cpu_reg].q ^= src.q; in opPXOR_a32()
H A Dx86_ops_bit.h6 cpu_state.eaaddr += ((cpu_state.regs[cpu_reg].w / 16) * 2); eal_r = 0; in opBT_w_r_a16()
9 if (temp & (1 << (cpu_state.regs[cpu_reg].w & 15))) flags |= C_FLAG; in opBT_w_r_a16()
21 cpu_state.eaaddr += ((cpu_state.regs[cpu_reg].w / 16) * 2); eal_r = 0; in opBT_w_r_a32()
24 if (temp & (1 << (cpu_state.regs[cpu_reg].w & 15))) flags |= C_FLAG; in opBT_w_r_a32()
36 cpu_state.eaaddr += ((cpu_state.regs[cpu_reg].l / 32) * 4); eal_r = 0; in opBT_l_r_a16()
39 if (temp & (1 << (cpu_state.regs[cpu_reg].l & 31))) flags |= C_FLAG; in opBT_l_r_a16()
51 cpu_state.eaaddr += ((cpu_state.regs[cpu_reg].l / 32) * 4); eal_r = 0; in opBT_l_r_a32()
54 if (temp & (1 << (cpu_state.regs[cpu_reg].l & 31))) flags |= C_FLAG; in opBT_l_r_a32()
71 tempc = (temp & (1 << (cpu_state.regs[cpu_reg].w & 15))) ? 1 : 0; \
72 temp operation (1 << (cpu_state.regs[cpu_reg].w & 15)); \
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H A Dx86_ops_arith.h279 setsub8(dst, getr8(cpu_reg)); in opCMP_b_rmw_a16()
290 setsub8(dst, getr8(cpu_reg)); in opCMP_b_rmw_a32()
302 setsub16(dst, cpu_state.regs[cpu_reg].w); in opCMP_w_rmw_a16()
348 setsub8(getr8(cpu_reg), src); in opCMP_b_rm_a16()
358 setsub8(getr8(cpu_reg), src); in opCMP_b_rm_a32()
438 temp2 = getr8(cpu_reg); in opTEST_b_a16()
450 temp2 = getr8(cpu_reg); in opTEST_b_a32()
463 temp2 = cpu_state.regs[cpu_reg].w; in opTEST_w_a16()
475 temp2 = cpu_state.regs[cpu_reg].w; in opTEST_w_a32()
488 temp2 = cpu_state.regs[cpu_reg].l; in opTEST_l_a16()
[all …]
H A Dx86_ops_mov.h431 setr8(cpu_rm, getr8(cpu_reg)); in opMOV_b_r_a16()
438 seteab(getr8(cpu_reg)); in opMOV_b_r_a16()
449 setr8(cpu_rm, getr8(cpu_reg)); in opMOV_b_r_a32()
456 seteab(getr8(cpu_reg)); in opMOV_b_r_a32()
540 setr8(cpu_reg, getr8(cpu_rm)); in opMOV_r_b_a16()
549 setr8(cpu_reg, temp); in opMOV_r_b_a16()
560 setr8(cpu_reg, getr8(cpu_rm)); in opMOV_r_b_a32()
569 setr8(cpu_reg, temp); in opMOV_r_b_a32()
589 cpu_state.regs[cpu_reg].w = temp; in opMOV_r_w_a16()
609 cpu_state.regs[cpu_reg].w = temp; in opMOV_r_w_a32()
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H A Dx86_ops_mul.h15 cpu_state.regs[cpu_reg].w = templ & 0xffff; in opIMUL_w_iw_a16()
35 cpu_state.regs[cpu_reg].w = templ & 0xffff; in opIMUL_w_iw_a32()
56 cpu_state.regs[cpu_reg].l = temp64 & 0xffffffff; in opIMUL_l_il_a16()
76 cpu_state.regs[cpu_reg].l = temp64 & 0xffffffff; in opIMUL_l_il_a32()
98 cpu_state.regs[cpu_reg].w = templ & 0xffff; in opIMUL_w_ib_a16()
119 cpu_state.regs[cpu_reg].w = templ & 0xffff; in opIMUL_w_ib_a32()
140 cpu_state.regs[cpu_reg].l = temp64 & 0xffffffff; in opIMUL_l_ib_a16()
160 cpu_state.regs[cpu_reg].l = temp64 & 0xffffffff; in opIMUL_l_ib_a32()
176 cpu_state.regs[cpu_reg].w = templ & 0xFFFF; in opIMUL_w_w_a16()
192 cpu_state.regs[cpu_reg].w = templ & 0xFFFF; in opIMUL_w_w_a32()
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H A Dx86_ops_xchg.h6 seteab(getr8(cpu_reg)); if (cpu_state.abrt) return 1; in opXCHG_b_a16()
7 setr8(cpu_reg, temp); in opXCHG_b_a16()
17 seteab(getr8(cpu_reg)); if (cpu_state.abrt) return 1; in opXCHG_b_a32()
18 setr8(cpu_reg, temp); in opXCHG_b_a32()
29 seteaw(cpu_state.regs[cpu_reg].w); if (cpu_state.abrt) return 1; in opXCHG_w_a16()
30 cpu_state.regs[cpu_reg].w = temp; in opXCHG_w_a16()
40 seteaw(cpu_state.regs[cpu_reg].w); if (cpu_state.abrt) return 1; in opXCHG_w_a32()
41 cpu_state.regs[cpu_reg].w = temp; in opXCHG_w_a32()
52 seteal(cpu_state.regs[cpu_reg].l); if (cpu_state.abrt) return 1; in opXCHG_l_a16()
53 cpu_state.regs[cpu_reg].l = temp; in opXCHG_l_a16()
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H A Dx86_ops_mov_ctrl.h10 switch (cpu_reg) in opMOV_r_CRx_a16()
30 pclog("Bad read of CR%i %i\n",rmdat&7,cpu_reg); in opMOV_r_CRx_a16()
48 switch (cpu_reg) in opMOV_r_CRx_a32()
87 cpu_state.regs[cpu_rm].l = dr[cpu_reg]; in opMOV_r_DRx_a16()
101 cpu_state.regs[cpu_rm].l = dr[cpu_reg]; in opMOV_r_DRx_a32()
118 switch (cpu_reg) in opMOV_CRx_r_a16()
154 pclog("Bad load CR%i\n", cpu_reg); in opMOV_CRx_r_a16()
174 switch (cpu_reg) in opMOV_CRx_r_a32()
210 pclog("Bad load CR%i\n", cpu_reg); in opMOV_CRx_r_a32()
229 dr[cpu_reg] = cpu_state.regs[cpu_rm].l; in opMOV_DRx_r_a16()
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/dports/multimedia/v4l-utils/linux-5.13-rc2/arch/arm64/kvm/hyp/nvhe/
H A Dhyp-main.c28 cpu_reg(host_ctxt, 1) = __kvm_vcpu_run(kern_hyp_va(vcpu)); in handle___kvm_vcpu_run()
61 __kvm_timer_set_cntvoff(cpu_reg(host_ctxt, 1)); in handle___kvm_timer_set_cntvoff()
75 cpu_reg(host_ctxt, 1) = __vgic_v3_get_gic_config(); in handle___vgic_v3_get_gic_config()
80 cpu_reg(host_ctxt, 1) = __vgic_v3_read_vmcr(); in handle___vgic_v3_read_vmcr()
85 __vgic_v3_write_vmcr(cpu_reg(host_ctxt, 1)); in handle___vgic_v3_write_vmcr()
95 cpu_reg(host_ctxt, 1) = __kvm_get_mdcr_el2(); in handle___kvm_get_mdcr_el2()
133 cpu_reg(host_ctxt, 1) = pkvm_cpu_set_vector(slot); in handle___pkvm_cpu_set_vector()
157 cpu_reg(host_ctxt, 1) = __pkvm_prot_finalize(); in handle___pkvm_prot_finalize()
165 cpu_reg(host_ctxt, 1) = __pkvm_mark_hyp(start, end); in handle___pkvm_mark_hyp()
208 cpu_reg(host_ctxt, 0) = SMCCC_RET_SUCCESS; in handle_host_hcall()
[all …]
/dports/multimedia/v4l_compat/linux-5.13-rc2/arch/arm64/kvm/hyp/nvhe/
H A Dhyp-main.c28 cpu_reg(host_ctxt, 1) = __kvm_vcpu_run(kern_hyp_va(vcpu)); in handle___kvm_vcpu_run()
61 __kvm_timer_set_cntvoff(cpu_reg(host_ctxt, 1)); in handle___kvm_timer_set_cntvoff()
75 cpu_reg(host_ctxt, 1) = __vgic_v3_get_gic_config(); in handle___vgic_v3_get_gic_config()
80 cpu_reg(host_ctxt, 1) = __vgic_v3_read_vmcr(); in handle___vgic_v3_read_vmcr()
85 __vgic_v3_write_vmcr(cpu_reg(host_ctxt, 1)); in handle___vgic_v3_write_vmcr()
95 cpu_reg(host_ctxt, 1) = __kvm_get_mdcr_el2(); in handle___kvm_get_mdcr_el2()
133 cpu_reg(host_ctxt, 1) = pkvm_cpu_set_vector(slot); in handle___pkvm_cpu_set_vector()
157 cpu_reg(host_ctxt, 1) = __pkvm_prot_finalize(); in handle___pkvm_prot_finalize()
165 cpu_reg(host_ctxt, 1) = __pkvm_mark_hyp(start, end); in handle___pkvm_mark_hyp()
208 cpu_reg(host_ctxt, 0) = SMCCC_RET_SUCCESS; in handle_host_hcall()
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/dports/multimedia/libv4l/linux-5.13-rc2/arch/arm64/kvm/hyp/nvhe/
H A Dhyp-main.c28 cpu_reg(host_ctxt, 1) = __kvm_vcpu_run(kern_hyp_va(vcpu)); in handle___kvm_vcpu_run()
61 __kvm_timer_set_cntvoff(cpu_reg(host_ctxt, 1)); in handle___kvm_timer_set_cntvoff()
75 cpu_reg(host_ctxt, 1) = __vgic_v3_get_gic_config(); in handle___vgic_v3_get_gic_config()
80 cpu_reg(host_ctxt, 1) = __vgic_v3_read_vmcr(); in handle___vgic_v3_read_vmcr()
85 __vgic_v3_write_vmcr(cpu_reg(host_ctxt, 1)); in handle___vgic_v3_write_vmcr()
95 cpu_reg(host_ctxt, 1) = __kvm_get_mdcr_el2(); in handle___kvm_get_mdcr_el2()
133 cpu_reg(host_ctxt, 1) = pkvm_cpu_set_vector(slot); in handle___pkvm_cpu_set_vector()
157 cpu_reg(host_ctxt, 1) = __pkvm_prot_finalize(); in handle___pkvm_prot_finalize()
165 cpu_reg(host_ctxt, 1) = __pkvm_mark_hyp(start, end); in handle___pkvm_mark_hyp()
208 cpu_reg(host_ctxt, 0) = SMCCC_RET_SUCCESS; in handle_host_hcall()
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/dports/emulators/qemu60/qemu-6.0.0/roms/ipxe/src/drivers/net/
H A Dbnx2.c1353 load_cpu_fw(struct bnx2 *bp, struct cpu_reg *cpu_reg, struct fw_info *fw) in load_cpu_fw() argument
1362 REG_WR_IND(bp, cpu_reg->state, cpu_reg->state_value_clear); in load_cpu_fw()
1365 offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base); in load_cpu_fw()
1375 offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base); in load_cpu_fw()
1385 offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base); in load_cpu_fw()
1395 offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base); in load_cpu_fw()
1405 offset = cpu_reg->spad_base + in load_cpu_fw()
1422 REG_WR_IND(bp, cpu_reg->state, cpu_reg->state_value_clear); in load_cpu_fw()
1429 struct cpu_reg cpu_reg; in bnx2_init_cpus() local
1485 load_cpu_fw(bp, &cpu_reg, &fw); in bnx2_init_cpus()
[all …]
/dports/emulators/qemu42/qemu-4.2.1/roms/ipxe/src/drivers/net/
H A Dbnx2.c1353 load_cpu_fw(struct bnx2 *bp, struct cpu_reg *cpu_reg, struct fw_info *fw) in load_cpu_fw() argument
1362 REG_WR_IND(bp, cpu_reg->state, cpu_reg->state_value_clear); in load_cpu_fw()
1365 offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base); in load_cpu_fw()
1375 offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base); in load_cpu_fw()
1385 offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base); in load_cpu_fw()
1395 offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base); in load_cpu_fw()
1405 offset = cpu_reg->spad_base + in load_cpu_fw()
1422 REG_WR_IND(bp, cpu_reg->state, cpu_reg->state_value_clear); in load_cpu_fw()
1429 struct cpu_reg cpu_reg; in bnx2_init_cpus() local
1485 load_cpu_fw(bp, &cpu_reg, &fw); in bnx2_init_cpus()
[all …]
/dports/emulators/qemu-utils/qemu-4.2.1/roms/ipxe/src/drivers/net/
H A Dbnx2.c1353 load_cpu_fw(struct bnx2 *bp, struct cpu_reg *cpu_reg, struct fw_info *fw) in load_cpu_fw() argument
1362 REG_WR_IND(bp, cpu_reg->state, cpu_reg->state_value_clear); in load_cpu_fw()
1365 offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base); in load_cpu_fw()
1375 offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base); in load_cpu_fw()
1385 offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base); in load_cpu_fw()
1395 offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base); in load_cpu_fw()
1405 offset = cpu_reg->spad_base + in load_cpu_fw()
1422 REG_WR_IND(bp, cpu_reg->state, cpu_reg->state_value_clear); in load_cpu_fw()
1429 struct cpu_reg cpu_reg; in bnx2_init_cpus() local
1485 load_cpu_fw(bp, &cpu_reg, &fw); in bnx2_init_cpus()
[all …]
/dports/emulators/qemu-powernv/qemu-powernv-3.0.50/roms/ipxe/src/drivers/net/
H A Dbnx2.c1353 load_cpu_fw(struct bnx2 *bp, struct cpu_reg *cpu_reg, struct fw_info *fw) in load_cpu_fw() argument
1362 REG_WR_IND(bp, cpu_reg->state, cpu_reg->state_value_clear); in load_cpu_fw()
1365 offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base); in load_cpu_fw()
1375 offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base); in load_cpu_fw()
1385 offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base); in load_cpu_fw()
1395 offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base); in load_cpu_fw()
1405 offset = cpu_reg->spad_base + in load_cpu_fw()
1422 REG_WR_IND(bp, cpu_reg->state, cpu_reg->state_value_clear); in load_cpu_fw()
1429 struct cpu_reg cpu_reg; in bnx2_init_cpus() local
1485 load_cpu_fw(bp, &cpu_reg, &fw); in bnx2_init_cpus()
[all …]
/dports/sysutils/syslinux/syslinux-6.03/gpxe/src/drivers/net/
H A Dbnx2.c1353 load_cpu_fw(struct bnx2 *bp, struct cpu_reg *cpu_reg, struct fw_info *fw) in load_cpu_fw() argument
1362 REG_WR_IND(bp, cpu_reg->state, cpu_reg->state_value_clear); in load_cpu_fw()
1365 offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base); in load_cpu_fw()
1375 offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base); in load_cpu_fw()
1385 offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base); in load_cpu_fw()
1395 offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base); in load_cpu_fw()
1405 offset = cpu_reg->spad_base + in load_cpu_fw()
1422 REG_WR_IND(bp, cpu_reg->state, cpu_reg->state_value_clear); in load_cpu_fw()
1429 struct cpu_reg cpu_reg; in bnx2_init_cpus() local
1485 load_cpu_fw(bp, &cpu_reg, &fw); in bnx2_init_cpus()
[all …]
/dports/emulators/qemu5/qemu-5.2.0/roms/ipxe/src/drivers/net/
H A Dbnx2.c1353 load_cpu_fw(struct bnx2 *bp, struct cpu_reg *cpu_reg, struct fw_info *fw) in load_cpu_fw() argument
1362 REG_WR_IND(bp, cpu_reg->state, cpu_reg->state_value_clear); in load_cpu_fw()
1365 offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base); in load_cpu_fw()
1375 offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base); in load_cpu_fw()
1385 offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base); in load_cpu_fw()
1395 offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base); in load_cpu_fw()
1405 offset = cpu_reg->spad_base + in load_cpu_fw()
1422 REG_WR_IND(bp, cpu_reg->state, cpu_reg->state_value_clear); in load_cpu_fw()
1429 struct cpu_reg cpu_reg; in bnx2_init_cpus() local
1485 load_cpu_fw(bp, &cpu_reg, &fw); in bnx2_init_cpus()
[all …]
/dports/net/ipxe/ipxe-2265a65/src/drivers/net/
H A Dbnx2.c1353 load_cpu_fw(struct bnx2 *bp, struct cpu_reg *cpu_reg, struct fw_info *fw) in load_cpu_fw() argument
1362 REG_WR_IND(bp, cpu_reg->state, cpu_reg->state_value_clear); in load_cpu_fw()
1365 offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base); in load_cpu_fw()
1375 offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base); in load_cpu_fw()
1385 offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base); in load_cpu_fw()
1395 offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base); in load_cpu_fw()
1405 offset = cpu_reg->spad_base + in load_cpu_fw()
1422 REG_WR_IND(bp, cpu_reg->state, cpu_reg->state_value_clear); in load_cpu_fw()
1429 struct cpu_reg cpu_reg; in bnx2_init_cpus() local
1485 load_cpu_fw(bp, &cpu_reg, &fw); in bnx2_init_cpus()
[all …]
/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/ipxe/src/drivers/net/
H A Dbnx2.c1353 load_cpu_fw(struct bnx2 *bp, struct cpu_reg *cpu_reg, struct fw_info *fw) in load_cpu_fw() argument
1362 REG_WR_IND(bp, cpu_reg->state, cpu_reg->state_value_clear); in load_cpu_fw()
1365 offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base); in load_cpu_fw()
1375 offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base); in load_cpu_fw()
1385 offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base); in load_cpu_fw()
1395 offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base); in load_cpu_fw()
1405 offset = cpu_reg->spad_base + in load_cpu_fw()
1422 REG_WR_IND(bp, cpu_reg->state, cpu_reg->state_value_clear); in load_cpu_fw()
1429 struct cpu_reg cpu_reg; in bnx2_init_cpus() local
1485 load_cpu_fw(bp, &cpu_reg, &fw); in bnx2_init_cpus()
[all …]

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