| /dports/devel/libffcall/libffcall-2.4/avcall/ |
| H A D | avcall-powerpc-macos.s | 18 bge- cr0,L87
27 blt+ cr0,L6
33 beq- cr0,L8
35 beq- cr0,L11
37 beq- cr0,L14
39 beq- cr0,L17
41 beq- cr0,L20
43 beq- cr0,L23
45 beq- cr0,L26
47 beq- cr0,L29
[all …]
|
| /dports/graphics/libosmesa-gallium/mesa-21.3.6/src/intel/tools/tests/gen9/ |
| H A D | cr0.asm | 1 and(1) cr0<1>UD cr0<0,1,0>UD 0xfffffb3fUD { align1 1N switch };
2 and(1) cr0<1>UD cr0<0,1,0>UD 0xffffff3fUD { align1 1N switch };
3 and(1) cr0<1>UD cr0<0,1,0>UD 0xfffffb7fUD { align1 1N switch };
4 and(1) cr0<1>UD cr0<0,1,0>UD 0xffffff7fUD { align1 1N switch };
5 and(1) cr0<1>UD cr0<0,1,0>UD 0xfffffbbfUD { align1 1N switch };
6 and(1) cr0<1>UD cr0<0,1,0>UD 0xffffffbfUD { align1 1N switch };
7 and(1) cr0<1>UD cr0<0,1,0>UD 0xffffffcfUD { align1 1N switch };
8 and(1) cr0<1>UD cr0<0,1,0>UD 0xfffffbffUD { align1 1N switch };
9 or(1) cr0<1>UD cr0<0,1,0>UD 0x00000400UD { align1 1N switch };
10 or(1) cr0<1>UD cr0<0,1,0>UD 0x00000030UD { align1 1N switch };
[all …]
|
| /dports/lang/clover/mesa-21.3.6/src/intel/tools/tests/gen8/ |
| H A D | cr0.asm | 1 and(1) cr0<1>UD cr0<0,1,0>UD 0xfffffb3fUD { align1 1N switch };
2 and(1) cr0<1>UD cr0<0,1,0>UD 0xffffff3fUD { align1 1N switch };
3 and(1) cr0<1>UD cr0<0,1,0>UD 0xfffffb7fUD { align1 1N switch };
4 and(1) cr0<1>UD cr0<0,1,0>UD 0xffffff7fUD { align1 1N switch };
5 and(1) cr0<1>UD cr0<0,1,0>UD 0xfffffbbfUD { align1 1N switch };
6 and(1) cr0<1>UD cr0<0,1,0>UD 0xffffffbfUD { align1 1N switch };
7 and(1) cr0<1>UD cr0<0,1,0>UD 0xffffffcfUD { align1 1N switch };
8 and(1) cr0<1>UD cr0<0,1,0>UD 0xfffffbffUD { align1 1N switch };
9 or(1) cr0<1>UD cr0<0,1,0>UD 0x00000400UD { align1 1N switch };
10 or(1) cr0<1>UD cr0<0,1,0>UD 0x00000030UD { align1 1N switch };
[all …]
|
| /dports/lang/clover/mesa-21.3.6/src/intel/tools/tests/gen9/ |
| H A D | cr0.asm | 1 and(1) cr0<1>UD cr0<0,1,0>UD 0xfffffb3fUD { align1 1N switch };
2 and(1) cr0<1>UD cr0<0,1,0>UD 0xffffff3fUD { align1 1N switch };
3 and(1) cr0<1>UD cr0<0,1,0>UD 0xfffffb7fUD { align1 1N switch };
4 and(1) cr0<1>UD cr0<0,1,0>UD 0xffffff7fUD { align1 1N switch };
5 and(1) cr0<1>UD cr0<0,1,0>UD 0xfffffbbfUD { align1 1N switch };
6 and(1) cr0<1>UD cr0<0,1,0>UD 0xffffffbfUD { align1 1N switch };
7 and(1) cr0<1>UD cr0<0,1,0>UD 0xffffffcfUD { align1 1N switch };
8 and(1) cr0<1>UD cr0<0,1,0>UD 0xfffffbffUD { align1 1N switch };
9 or(1) cr0<1>UD cr0<0,1,0>UD 0x00000400UD { align1 1N switch };
10 or(1) cr0<1>UD cr0<0,1,0>UD 0x00000030UD { align1 1N switch };
[all …]
|
| /dports/graphics/libosmesa-gallium/mesa-21.3.6/src/intel/tools/tests/gen8/ |
| H A D | cr0.asm | 1 and(1) cr0<1>UD cr0<0,1,0>UD 0xfffffb3fUD { align1 1N switch };
2 and(1) cr0<1>UD cr0<0,1,0>UD 0xffffff3fUD { align1 1N switch };
3 and(1) cr0<1>UD cr0<0,1,0>UD 0xfffffb7fUD { align1 1N switch };
4 and(1) cr0<1>UD cr0<0,1,0>UD 0xffffff7fUD { align1 1N switch };
5 and(1) cr0<1>UD cr0<0,1,0>UD 0xfffffbbfUD { align1 1N switch };
6 and(1) cr0<1>UD cr0<0,1,0>UD 0xffffffbfUD { align1 1N switch };
7 and(1) cr0<1>UD cr0<0,1,0>UD 0xffffffcfUD { align1 1N switch };
8 and(1) cr0<1>UD cr0<0,1,0>UD 0xfffffbffUD { align1 1N switch };
9 or(1) cr0<1>UD cr0<0,1,0>UD 0x00000400UD { align1 1N switch };
10 or(1) cr0<1>UD cr0<0,1,0>UD 0x00000030UD { align1 1N switch };
[all …]
|
| /dports/graphics/libosmesa/mesa-21.3.6/src/intel/tools/tests/gen9/ |
| H A D | cr0.asm | 1 and(1) cr0<1>UD cr0<0,1,0>UD 0xfffffb3fUD { align1 1N switch };
2 and(1) cr0<1>UD cr0<0,1,0>UD 0xffffff3fUD { align1 1N switch };
3 and(1) cr0<1>UD cr0<0,1,0>UD 0xfffffb7fUD { align1 1N switch };
4 and(1) cr0<1>UD cr0<0,1,0>UD 0xffffff7fUD { align1 1N switch };
5 and(1) cr0<1>UD cr0<0,1,0>UD 0xfffffbbfUD { align1 1N switch };
6 and(1) cr0<1>UD cr0<0,1,0>UD 0xffffffbfUD { align1 1N switch };
7 and(1) cr0<1>UD cr0<0,1,0>UD 0xffffffcfUD { align1 1N switch };
8 and(1) cr0<1>UD cr0<0,1,0>UD 0xfffffbffUD { align1 1N switch };
9 or(1) cr0<1>UD cr0<0,1,0>UD 0x00000400UD { align1 1N switch };
10 or(1) cr0<1>UD cr0<0,1,0>UD 0x00000030UD { align1 1N switch };
[all …]
|
| /dports/graphics/libosmesa/mesa-21.3.6/src/intel/tools/tests/gen8/ |
| H A D | cr0.asm | 1 and(1) cr0<1>UD cr0<0,1,0>UD 0xfffffb3fUD { align1 1N switch };
2 and(1) cr0<1>UD cr0<0,1,0>UD 0xffffff3fUD { align1 1N switch };
3 and(1) cr0<1>UD cr0<0,1,0>UD 0xfffffb7fUD { align1 1N switch };
4 and(1) cr0<1>UD cr0<0,1,0>UD 0xffffff7fUD { align1 1N switch };
5 and(1) cr0<1>UD cr0<0,1,0>UD 0xfffffbbfUD { align1 1N switch };
6 and(1) cr0<1>UD cr0<0,1,0>UD 0xffffffbfUD { align1 1N switch };
7 and(1) cr0<1>UD cr0<0,1,0>UD 0xffffffcfUD { align1 1N switch };
8 and(1) cr0<1>UD cr0<0,1,0>UD 0xfffffbffUD { align1 1N switch };
9 or(1) cr0<1>UD cr0<0,1,0>UD 0x00000400UD { align1 1N switch };
10 or(1) cr0<1>UD cr0<0,1,0>UD 0x00000030UD { align1 1N switch };
[all …]
|
| /dports/graphics/mesa-libs/mesa-21.3.6/src/intel/tools/tests/gen9/ |
| H A D | cr0.asm | 1 and(1) cr0<1>UD cr0<0,1,0>UD 0xfffffb3fUD { align1 1N switch };
2 and(1) cr0<1>UD cr0<0,1,0>UD 0xffffff3fUD { align1 1N switch };
3 and(1) cr0<1>UD cr0<0,1,0>UD 0xfffffb7fUD { align1 1N switch };
4 and(1) cr0<1>UD cr0<0,1,0>UD 0xffffff7fUD { align1 1N switch };
5 and(1) cr0<1>UD cr0<0,1,0>UD 0xfffffbbfUD { align1 1N switch };
6 and(1) cr0<1>UD cr0<0,1,0>UD 0xffffffbfUD { align1 1N switch };
7 and(1) cr0<1>UD cr0<0,1,0>UD 0xffffffcfUD { align1 1N switch };
8 and(1) cr0<1>UD cr0<0,1,0>UD 0xfffffbffUD { align1 1N switch };
9 or(1) cr0<1>UD cr0<0,1,0>UD 0x00000400UD { align1 1N switch };
10 or(1) cr0<1>UD cr0<0,1,0>UD 0x00000030UD { align1 1N switch };
[all …]
|
| /dports/graphics/mesa-libs/mesa-21.3.6/src/intel/tools/tests/gen8/ |
| H A D | cr0.asm | 1 and(1) cr0<1>UD cr0<0,1,0>UD 0xfffffb3fUD { align1 1N switch };
2 and(1) cr0<1>UD cr0<0,1,0>UD 0xffffff3fUD { align1 1N switch };
3 and(1) cr0<1>UD cr0<0,1,0>UD 0xfffffb7fUD { align1 1N switch };
4 and(1) cr0<1>UD cr0<0,1,0>UD 0xffffff7fUD { align1 1N switch };
5 and(1) cr0<1>UD cr0<0,1,0>UD 0xfffffbbfUD { align1 1N switch };
6 and(1) cr0<1>UD cr0<0,1,0>UD 0xffffffbfUD { align1 1N switch };
7 and(1) cr0<1>UD cr0<0,1,0>UD 0xffffffcfUD { align1 1N switch };
8 and(1) cr0<1>UD cr0<0,1,0>UD 0xfffffbffUD { align1 1N switch };
9 or(1) cr0<1>UD cr0<0,1,0>UD 0x00000400UD { align1 1N switch };
10 or(1) cr0<1>UD cr0<0,1,0>UD 0x00000030UD { align1 1N switch };
[all …]
|
| /dports/graphics/mesa-gallium-xa/mesa-21.3.6/src/intel/tools/tests/gen8/ |
| H A D | cr0.asm | 1 and(1) cr0<1>UD cr0<0,1,0>UD 0xfffffb3fUD { align1 1N switch };
2 and(1) cr0<1>UD cr0<0,1,0>UD 0xffffff3fUD { align1 1N switch };
3 and(1) cr0<1>UD cr0<0,1,0>UD 0xfffffb7fUD { align1 1N switch };
4 and(1) cr0<1>UD cr0<0,1,0>UD 0xffffff7fUD { align1 1N switch };
5 and(1) cr0<1>UD cr0<0,1,0>UD 0xfffffbbfUD { align1 1N switch };
6 and(1) cr0<1>UD cr0<0,1,0>UD 0xffffffbfUD { align1 1N switch };
7 and(1) cr0<1>UD cr0<0,1,0>UD 0xffffffcfUD { align1 1N switch };
8 and(1) cr0<1>UD cr0<0,1,0>UD 0xfffffbffUD { align1 1N switch };
9 or(1) cr0<1>UD cr0<0,1,0>UD 0x00000400UD { align1 1N switch };
10 or(1) cr0<1>UD cr0<0,1,0>UD 0x00000030UD { align1 1N switch };
[all …]
|
| /dports/graphics/mesa-dri-classic/mesa-20.2.3/src/intel/tools/tests/gen8/ |
| H A D | cr0.asm | 1 and(1) cr0<1>UD cr0<0,1,0>UD 0xfffffb3fUD { align1 1N switch };
2 and(1) cr0<1>UD cr0<0,1,0>UD 0xffffff3fUD { align1 1N switch };
3 and(1) cr0<1>UD cr0<0,1,0>UD 0xfffffb7fUD { align1 1N switch };
4 and(1) cr0<1>UD cr0<0,1,0>UD 0xffffff7fUD { align1 1N switch };
5 and(1) cr0<1>UD cr0<0,1,0>UD 0xfffffbbfUD { align1 1N switch };
6 and(1) cr0<1>UD cr0<0,1,0>UD 0xffffffbfUD { align1 1N switch };
7 and(1) cr0<1>UD cr0<0,1,0>UD 0xffffffcfUD { align1 1N switch };
8 and(1) cr0<1>UD cr0<0,1,0>UD 0xfffffbffUD { align1 1N switch };
9 or(1) cr0<1>UD cr0<0,1,0>UD 0x00000400UD { align1 1N switch };
10 or(1) cr0<1>UD cr0<0,1,0>UD 0x00000030UD { align1 1N switch };
[all …]
|
| /dports/graphics/mesa-dri-gallium/mesa-21.3.6/src/intel/tools/tests/gen9/ |
| H A D | cr0.asm | 1 and(1) cr0<1>UD cr0<0,1,0>UD 0xfffffb3fUD { align1 1N switch };
2 and(1) cr0<1>UD cr0<0,1,0>UD 0xffffff3fUD { align1 1N switch };
3 and(1) cr0<1>UD cr0<0,1,0>UD 0xfffffb7fUD { align1 1N switch };
4 and(1) cr0<1>UD cr0<0,1,0>UD 0xffffff7fUD { align1 1N switch };
5 and(1) cr0<1>UD cr0<0,1,0>UD 0xfffffbbfUD { align1 1N switch };
6 and(1) cr0<1>UD cr0<0,1,0>UD 0xffffffbfUD { align1 1N switch };
7 and(1) cr0<1>UD cr0<0,1,0>UD 0xffffffcfUD { align1 1N switch };
8 and(1) cr0<1>UD cr0<0,1,0>UD 0xfffffbffUD { align1 1N switch };
9 or(1) cr0<1>UD cr0<0,1,0>UD 0x00000400UD { align1 1N switch };
10 or(1) cr0<1>UD cr0<0,1,0>UD 0x00000030UD { align1 1N switch };
[all …]
|
| /dports/graphics/mesa-dri-gallium/mesa-21.3.6/src/intel/tools/tests/gen8/ |
| H A D | cr0.asm | 1 and(1) cr0<1>UD cr0<0,1,0>UD 0xfffffb3fUD { align1 1N switch };
2 and(1) cr0<1>UD cr0<0,1,0>UD 0xffffff3fUD { align1 1N switch };
3 and(1) cr0<1>UD cr0<0,1,0>UD 0xfffffb7fUD { align1 1N switch };
4 and(1) cr0<1>UD cr0<0,1,0>UD 0xffffff7fUD { align1 1N switch };
5 and(1) cr0<1>UD cr0<0,1,0>UD 0xfffffbbfUD { align1 1N switch };
6 and(1) cr0<1>UD cr0<0,1,0>UD 0xffffffbfUD { align1 1N switch };
7 and(1) cr0<1>UD cr0<0,1,0>UD 0xffffffcfUD { align1 1N switch };
8 and(1) cr0<1>UD cr0<0,1,0>UD 0xfffffbffUD { align1 1N switch };
9 or(1) cr0<1>UD cr0<0,1,0>UD 0x00000400UD { align1 1N switch };
10 or(1) cr0<1>UD cr0<0,1,0>UD 0x00000030UD { align1 1N switch };
[all …]
|
| /dports/graphics/mesa-gallium-va/mesa-21.3.6/src/intel/tools/tests/gen9/ |
| H A D | cr0.asm | 1 and(1) cr0<1>UD cr0<0,1,0>UD 0xfffffb3fUD { align1 1N switch };
2 and(1) cr0<1>UD cr0<0,1,0>UD 0xffffff3fUD { align1 1N switch };
3 and(1) cr0<1>UD cr0<0,1,0>UD 0xfffffb7fUD { align1 1N switch };
4 and(1) cr0<1>UD cr0<0,1,0>UD 0xffffff7fUD { align1 1N switch };
5 and(1) cr0<1>UD cr0<0,1,0>UD 0xfffffbbfUD { align1 1N switch };
6 and(1) cr0<1>UD cr0<0,1,0>UD 0xffffffbfUD { align1 1N switch };
7 and(1) cr0<1>UD cr0<0,1,0>UD 0xffffffcfUD { align1 1N switch };
8 and(1) cr0<1>UD cr0<0,1,0>UD 0xfffffbffUD { align1 1N switch };
9 or(1) cr0<1>UD cr0<0,1,0>UD 0x00000400UD { align1 1N switch };
10 or(1) cr0<1>UD cr0<0,1,0>UD 0x00000030UD { align1 1N switch };
[all …]
|
| /dports/graphics/mesa-gallium-va/mesa-21.3.6/src/intel/tools/tests/gen8/ |
| H A D | cr0.asm | 1 and(1) cr0<1>UD cr0<0,1,0>UD 0xfffffb3fUD { align1 1N switch };
2 and(1) cr0<1>UD cr0<0,1,0>UD 0xffffff3fUD { align1 1N switch };
3 and(1) cr0<1>UD cr0<0,1,0>UD 0xfffffb7fUD { align1 1N switch };
4 and(1) cr0<1>UD cr0<0,1,0>UD 0xffffff7fUD { align1 1N switch };
5 and(1) cr0<1>UD cr0<0,1,0>UD 0xfffffbbfUD { align1 1N switch };
6 and(1) cr0<1>UD cr0<0,1,0>UD 0xffffffbfUD { align1 1N switch };
7 and(1) cr0<1>UD cr0<0,1,0>UD 0xffffffcfUD { align1 1N switch };
8 and(1) cr0<1>UD cr0<0,1,0>UD 0xfffffbffUD { align1 1N switch };
9 or(1) cr0<1>UD cr0<0,1,0>UD 0x00000400UD { align1 1N switch };
10 or(1) cr0<1>UD cr0<0,1,0>UD 0x00000030UD { align1 1N switch };
[all …]
|
| /dports/graphics/mesa-gallium-vdpau/mesa-21.3.6/src/intel/tools/tests/gen8/ |
| H A D | cr0.asm | 1 and(1) cr0<1>UD cr0<0,1,0>UD 0xfffffb3fUD { align1 1N switch };
2 and(1) cr0<1>UD cr0<0,1,0>UD 0xffffff3fUD { align1 1N switch };
3 and(1) cr0<1>UD cr0<0,1,0>UD 0xfffffb7fUD { align1 1N switch };
4 and(1) cr0<1>UD cr0<0,1,0>UD 0xffffff7fUD { align1 1N switch };
5 and(1) cr0<1>UD cr0<0,1,0>UD 0xfffffbbfUD { align1 1N switch };
6 and(1) cr0<1>UD cr0<0,1,0>UD 0xffffffbfUD { align1 1N switch };
7 and(1) cr0<1>UD cr0<0,1,0>UD 0xffffffcfUD { align1 1N switch };
8 and(1) cr0<1>UD cr0<0,1,0>UD 0xfffffbffUD { align1 1N switch };
9 or(1) cr0<1>UD cr0<0,1,0>UD 0x00000400UD { align1 1N switch };
10 or(1) cr0<1>UD cr0<0,1,0>UD 0x00000030UD { align1 1N switch };
[all …]
|
| /dports/graphics/mesa-gallium-xa/mesa-21.3.6/src/intel/tools/tests/gen9/ |
| H A D | cr0.asm | 1 and(1) cr0<1>UD cr0<0,1,0>UD 0xfffffb3fUD { align1 1N switch };
2 and(1) cr0<1>UD cr0<0,1,0>UD 0xffffff3fUD { align1 1N switch };
3 and(1) cr0<1>UD cr0<0,1,0>UD 0xfffffb7fUD { align1 1N switch };
4 and(1) cr0<1>UD cr0<0,1,0>UD 0xffffff7fUD { align1 1N switch };
5 and(1) cr0<1>UD cr0<0,1,0>UD 0xfffffbbfUD { align1 1N switch };
6 and(1) cr0<1>UD cr0<0,1,0>UD 0xffffffbfUD { align1 1N switch };
7 and(1) cr0<1>UD cr0<0,1,0>UD 0xffffffcfUD { align1 1N switch };
8 and(1) cr0<1>UD cr0<0,1,0>UD 0xfffffbffUD { align1 1N switch };
9 or(1) cr0<1>UD cr0<0,1,0>UD 0x00000400UD { align1 1N switch };
10 or(1) cr0<1>UD cr0<0,1,0>UD 0x00000030UD { align1 1N switch };
[all …]
|
| /dports/graphics/mesa-gallium-vdpau/mesa-21.3.6/src/intel/tools/tests/gen9/ |
| H A D | cr0.asm | 1 and(1) cr0<1>UD cr0<0,1,0>UD 0xfffffb3fUD { align1 1N switch };
2 and(1) cr0<1>UD cr0<0,1,0>UD 0xffffff3fUD { align1 1N switch };
3 and(1) cr0<1>UD cr0<0,1,0>UD 0xfffffb7fUD { align1 1N switch };
4 and(1) cr0<1>UD cr0<0,1,0>UD 0xffffff7fUD { align1 1N switch };
5 and(1) cr0<1>UD cr0<0,1,0>UD 0xfffffbbfUD { align1 1N switch };
6 and(1) cr0<1>UD cr0<0,1,0>UD 0xffffffbfUD { align1 1N switch };
7 and(1) cr0<1>UD cr0<0,1,0>UD 0xffffffcfUD { align1 1N switch };
8 and(1) cr0<1>UD cr0<0,1,0>UD 0xfffffbffUD { align1 1N switch };
9 or(1) cr0<1>UD cr0<0,1,0>UD 0x00000400UD { align1 1N switch };
10 or(1) cr0<1>UD cr0<0,1,0>UD 0x00000030UD { align1 1N switch };
[all …]
|
| /dports/graphics/mesa-devel/mesa-22.0-branchpoint-2059-ge8a63cf61ec/src/intel/tools/tests/gen8/ |
| H A D | cr0.asm | 1 and(1) cr0<1>UD cr0<0,1,0>UD 0xfffffb3fUD { align1 1N switch };
2 and(1) cr0<1>UD cr0<0,1,0>UD 0xffffff3fUD { align1 1N switch };
3 and(1) cr0<1>UD cr0<0,1,0>UD 0xfffffb7fUD { align1 1N switch };
4 and(1) cr0<1>UD cr0<0,1,0>UD 0xffffff7fUD { align1 1N switch };
5 and(1) cr0<1>UD cr0<0,1,0>UD 0xfffffbbfUD { align1 1N switch };
6 and(1) cr0<1>UD cr0<0,1,0>UD 0xffffffbfUD { align1 1N switch };
7 and(1) cr0<1>UD cr0<0,1,0>UD 0xffffffcfUD { align1 1N switch };
8 and(1) cr0<1>UD cr0<0,1,0>UD 0xfffffbffUD { align1 1N switch };
9 or(1) cr0<1>UD cr0<0,1,0>UD 0x00000400UD { align1 1N switch };
10 or(1) cr0<1>UD cr0<0,1,0>UD 0x00000030UD { align1 1N switch };
[all …]
|
| /dports/graphics/mesa-devel/mesa-22.0-branchpoint-2059-ge8a63cf61ec/src/intel/tools/tests/gen9/ |
| H A D | cr0.asm | 1 and(1) cr0<1>UD cr0<0,1,0>UD 0xfffffb3fUD { align1 1N switch };
2 and(1) cr0<1>UD cr0<0,1,0>UD 0xffffff3fUD { align1 1N switch };
3 and(1) cr0<1>UD cr0<0,1,0>UD 0xfffffb7fUD { align1 1N switch };
4 and(1) cr0<1>UD cr0<0,1,0>UD 0xffffff7fUD { align1 1N switch };
5 and(1) cr0<1>UD cr0<0,1,0>UD 0xfffffbbfUD { align1 1N switch };
6 and(1) cr0<1>UD cr0<0,1,0>UD 0xffffffbfUD { align1 1N switch };
7 and(1) cr0<1>UD cr0<0,1,0>UD 0xffffffcfUD { align1 1N switch };
8 and(1) cr0<1>UD cr0<0,1,0>UD 0xfffffbffUD { align1 1N switch };
9 or(1) cr0<1>UD cr0<0,1,0>UD 0x00000400UD { align1 1N switch };
10 or(1) cr0<1>UD cr0<0,1,0>UD 0x00000030UD { align1 1N switch };
[all …]
|
| /dports/graphics/mesa-dri-classic/mesa-20.2.3/src/intel/tools/tests/gen9/ |
| H A D | cr0.asm | 1 and(1) cr0<1>UD cr0<0,1,0>UD 0xfffffb3fUD { align1 1N switch };
2 and(1) cr0<1>UD cr0<0,1,0>UD 0xffffff3fUD { align1 1N switch };
3 and(1) cr0<1>UD cr0<0,1,0>UD 0xfffffb7fUD { align1 1N switch };
4 and(1) cr0<1>UD cr0<0,1,0>UD 0xffffff7fUD { align1 1N switch };
5 and(1) cr0<1>UD cr0<0,1,0>UD 0xfffffbbfUD { align1 1N switch };
6 and(1) cr0<1>UD cr0<0,1,0>UD 0xffffffbfUD { align1 1N switch };
7 and(1) cr0<1>UD cr0<0,1,0>UD 0xffffffcfUD { align1 1N switch };
8 and(1) cr0<1>UD cr0<0,1,0>UD 0xfffffbffUD { align1 1N switch };
9 or(1) cr0<1>UD cr0<0,1,0>UD 0x00000400UD { align1 1N switch };
10 or(1) cr0<1>UD cr0<0,1,0>UD 0x00000030UD { align1 1N switch };
[all …]
|
| /dports/graphics/mesa-dri/mesa-21.3.6/src/intel/tools/tests/gen9/ |
| H A D | cr0.asm | 1 and(1) cr0<1>UD cr0<0,1,0>UD 0xfffffb3fUD { align1 1N switch };
2 and(1) cr0<1>UD cr0<0,1,0>UD 0xffffff3fUD { align1 1N switch };
3 and(1) cr0<1>UD cr0<0,1,0>UD 0xfffffb7fUD { align1 1N switch };
4 and(1) cr0<1>UD cr0<0,1,0>UD 0xffffff7fUD { align1 1N switch };
5 and(1) cr0<1>UD cr0<0,1,0>UD 0xfffffbbfUD { align1 1N switch };
6 and(1) cr0<1>UD cr0<0,1,0>UD 0xffffffbfUD { align1 1N switch };
7 and(1) cr0<1>UD cr0<0,1,0>UD 0xffffffcfUD { align1 1N switch };
8 and(1) cr0<1>UD cr0<0,1,0>UD 0xfffffbffUD { align1 1N switch };
9 or(1) cr0<1>UD cr0<0,1,0>UD 0x00000400UD { align1 1N switch };
10 or(1) cr0<1>UD cr0<0,1,0>UD 0x00000030UD { align1 1N switch };
[all …]
|
| /dports/graphics/mesa-dri/mesa-21.3.6/src/intel/tools/tests/gen8/ |
| H A D | cr0.asm | 1 and(1) cr0<1>UD cr0<0,1,0>UD 0xfffffb3fUD { align1 1N switch };
2 and(1) cr0<1>UD cr0<0,1,0>UD 0xffffff3fUD { align1 1N switch };
3 and(1) cr0<1>UD cr0<0,1,0>UD 0xfffffb7fUD { align1 1N switch };
4 and(1) cr0<1>UD cr0<0,1,0>UD 0xffffff7fUD { align1 1N switch };
5 and(1) cr0<1>UD cr0<0,1,0>UD 0xfffffbbfUD { align1 1N switch };
6 and(1) cr0<1>UD cr0<0,1,0>UD 0xffffffbfUD { align1 1N switch };
7 and(1) cr0<1>UD cr0<0,1,0>UD 0xffffffcfUD { align1 1N switch };
8 and(1) cr0<1>UD cr0<0,1,0>UD 0xfffffbffUD { align1 1N switch };
9 or(1) cr0<1>UD cr0<0,1,0>UD 0x00000400UD { align1 1N switch };
10 or(1) cr0<1>UD cr0<0,1,0>UD 0x00000030UD { align1 1N switch };
[all …]
|
| /dports/devel/libffcall/libffcall-2.4/vacall/ |
| H A D | vacall-powerpc-macos.s | 49 beq- cr0,L1
51 beq- cr0,L41
53 beq- cr0,L41
55 beq- cr0,L42
57 beq- cr0,L43
59 beq- cr0,L44
61 beq- cr0,L40
63 beq- cr0,L40
87 bne+ cr0,L1
90 beq- cr0,L1
[all …]
|
| /dports/devel/libffcall/libffcall-2.4/callback/vacall_r/ |
| H A D | vacall-powerpc-macos.s | 44 beq- cr0,L1
46 beq- cr0,L41
48 beq- cr0,L41
50 beq- cr0,L42
52 beq- cr0,L43
54 beq- cr0,L44
56 beq- cr0,L40
58 beq- cr0,L40
82 bne+ cr0,L1
85 beq- cr0,L1
[all …]
|