| /dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/arch/arm/mach-rockchip/ |
| H A D | sdram.c | 80 u32 rank, cs0_col, bk, cs0_row, cs1_row, bw, row_3_4; in rockchip_sdram_size() local
109 cs0_row = 12; in rockchip_sdram_size()
111 cs0_row = 13 + (sys_reg2 >> in rockchip_sdram_size()
130 cs0_row = 13 + (sys_reg2 >> SYS_REG_CS0_ROW_SHIFT(ch) & in rockchip_sdram_size()
144 chipsize_mb = (1 << (cs0_row + cs0_col + bk + bg + bw - 20)); in rockchip_sdram_size()
147 chipsize_mb += chipsize_mb >> ((cs0_row - cs1_row) + in rockchip_sdram_size()
155 rank, cs0_col, cs1_col, bk, cs0_row, in rockchip_sdram_size()
160 rank, cs0_col, bk, cs0_row, in rockchip_sdram_size()
|
| /dports/sysutils/u-boot-olinuxino-lime2-emmc/u-boot-2021.07/arch/arm/mach-rockchip/ |
| H A D | sdram.c | 80 u32 rank, cs0_col, bk, cs0_row, cs1_row, bw, row_3_4; in rockchip_sdram_size() local
109 cs0_row = 12; in rockchip_sdram_size()
111 cs0_row = 13 + (sys_reg2 >> in rockchip_sdram_size()
130 cs0_row = 13 + (sys_reg2 >> SYS_REG_CS0_ROW_SHIFT(ch) & in rockchip_sdram_size()
144 chipsize_mb = (1 << (cs0_row + cs0_col + bk + bg + bw - 20)); in rockchip_sdram_size()
147 chipsize_mb += chipsize_mb >> ((cs0_row - cs1_row) + in rockchip_sdram_size()
155 rank, cs0_col, cs1_col, bk, cs0_row, in rockchip_sdram_size()
160 rank, cs0_col, bk, cs0_row, in rockchip_sdram_size()
|
| /dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/arch/arm/mach-rockchip/ |
| H A D | sdram.c | 80 u32 rank, cs0_col, bk, cs0_row, cs1_row, bw, row_3_4; in rockchip_sdram_size() local
109 cs0_row = 12; in rockchip_sdram_size()
111 cs0_row = 13 + (sys_reg2 >> in rockchip_sdram_size()
130 cs0_row = 13 + (sys_reg2 >> SYS_REG_CS0_ROW_SHIFT(ch) & in rockchip_sdram_size()
144 chipsize_mb = (1 << (cs0_row + cs0_col + bk + bg + bw - 20)); in rockchip_sdram_size()
147 chipsize_mb += chipsize_mb >> ((cs0_row - cs1_row) + in rockchip_sdram_size()
155 rank, cs0_col, cs1_col, bk, cs0_row, in rockchip_sdram_size()
160 rank, cs0_col, bk, cs0_row, in rockchip_sdram_size()
|
| /dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/arch/arm/mach-rockchip/ |
| H A D | sdram.c | 80 u32 rank, cs0_col, bk, cs0_row, cs1_row, bw, row_3_4; in rockchip_sdram_size() local
109 cs0_row = 12; in rockchip_sdram_size()
111 cs0_row = 13 + (sys_reg2 >> in rockchip_sdram_size()
130 cs0_row = 13 + (sys_reg2 >> SYS_REG_CS0_ROW_SHIFT(ch) & in rockchip_sdram_size()
144 chipsize_mb = (1 << (cs0_row + cs0_col + bk + bg + bw - 20)); in rockchip_sdram_size()
147 chipsize_mb += chipsize_mb >> ((cs0_row - cs1_row) + in rockchip_sdram_size()
155 rank, cs0_col, cs1_col, bk, cs0_row, in rockchip_sdram_size()
160 rank, cs0_col, bk, cs0_row, in rockchip_sdram_size()
|
| /dports/sysutils/u-boot-chip/u-boot-2021.07/arch/arm/mach-rockchip/ |
| H A D | sdram.c | 80 u32 rank, cs0_col, bk, cs0_row, cs1_row, bw, row_3_4; in rockchip_sdram_size() local
109 cs0_row = 12; in rockchip_sdram_size()
111 cs0_row = 13 + (sys_reg2 >> in rockchip_sdram_size()
130 cs0_row = 13 + (sys_reg2 >> SYS_REG_CS0_ROW_SHIFT(ch) & in rockchip_sdram_size()
144 chipsize_mb = (1 << (cs0_row + cs0_col + bk + bg + bw - 20)); in rockchip_sdram_size()
147 chipsize_mb += chipsize_mb >> ((cs0_row - cs1_row) + in rockchip_sdram_size()
155 rank, cs0_col, cs1_col, bk, cs0_row, in rockchip_sdram_size()
160 rank, cs0_col, bk, cs0_row, in rockchip_sdram_size()
|
| /dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/arch/arm/mach-rockchip/ |
| H A D | sdram.c | 80 u32 rank, cs0_col, bk, cs0_row, cs1_row, bw, row_3_4; in rockchip_sdram_size() local
109 cs0_row = 12; in rockchip_sdram_size()
111 cs0_row = 13 + (sys_reg2 >> in rockchip_sdram_size()
130 cs0_row = 13 + (sys_reg2 >> SYS_REG_CS0_ROW_SHIFT(ch) & in rockchip_sdram_size()
144 chipsize_mb = (1 << (cs0_row + cs0_col + bk + bg + bw - 20)); in rockchip_sdram_size()
147 chipsize_mb += chipsize_mb >> ((cs0_row - cs1_row) + in rockchip_sdram_size()
155 rank, cs0_col, cs1_col, bk, cs0_row, in rockchip_sdram_size()
160 rank, cs0_col, bk, cs0_row, in rockchip_sdram_size()
|
| /dports/sysutils/u-boot-sinovoip-bpi-m3/u-boot-2021.07/arch/arm/mach-rockchip/ |
| H A D | sdram.c | 80 u32 rank, cs0_col, bk, cs0_row, cs1_row, bw, row_3_4; in rockchip_sdram_size() local
109 cs0_row = 12; in rockchip_sdram_size()
111 cs0_row = 13 + (sys_reg2 >> in rockchip_sdram_size()
130 cs0_row = 13 + (sys_reg2 >> SYS_REG_CS0_ROW_SHIFT(ch) & in rockchip_sdram_size()
144 chipsize_mb = (1 << (cs0_row + cs0_col + bk + bg + bw - 20)); in rockchip_sdram_size()
147 chipsize_mb += chipsize_mb >> ((cs0_row - cs1_row) + in rockchip_sdram_size()
155 rank, cs0_col, cs1_col, bk, cs0_row, in rockchip_sdram_size()
160 rank, cs0_col, bk, cs0_row, in rockchip_sdram_size()
|
| /dports/sysutils/u-boot-a13-olinuxino/u-boot-2021.07/arch/arm/mach-rockchip/ |
| H A D | sdram.c | 80 u32 rank, cs0_col, bk, cs0_row, cs1_row, bw, row_3_4; in rockchip_sdram_size() local
109 cs0_row = 12; in rockchip_sdram_size()
111 cs0_row = 13 + (sys_reg2 >> in rockchip_sdram_size()
130 cs0_row = 13 + (sys_reg2 >> SYS_REG_CS0_ROW_SHIFT(ch) & in rockchip_sdram_size()
144 chipsize_mb = (1 << (cs0_row + cs0_col + bk + bg + bw - 20)); in rockchip_sdram_size()
147 chipsize_mb += chipsize_mb >> ((cs0_row - cs1_row) + in rockchip_sdram_size()
155 rank, cs0_col, cs1_col, bk, cs0_row, in rockchip_sdram_size()
160 rank, cs0_col, bk, cs0_row, in rockchip_sdram_size()
|
| /dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/arch/arm/mach-rockchip/ |
| H A D | sdram.c | 80 u32 rank, cs0_col, bk, cs0_row, cs1_row, bw, row_3_4; in rockchip_sdram_size() local
109 cs0_row = 12; in rockchip_sdram_size()
111 cs0_row = 13 + (sys_reg2 >> in rockchip_sdram_size()
130 cs0_row = 13 + (sys_reg2 >> SYS_REG_CS0_ROW_SHIFT(ch) & in rockchip_sdram_size()
144 chipsize_mb = (1 << (cs0_row + cs0_col + bk + bg + bw - 20)); in rockchip_sdram_size()
147 chipsize_mb += chipsize_mb >> ((cs0_row - cs1_row) + in rockchip_sdram_size()
155 rank, cs0_col, cs1_col, bk, cs0_row, in rockchip_sdram_size()
160 rank, cs0_col, bk, cs0_row, in rockchip_sdram_size()
|
| /dports/sysutils/u-boot-sopine-spi/u-boot-2021.07/arch/arm/mach-rockchip/ |
| H A D | sdram.c | 80 u32 rank, cs0_col, bk, cs0_row, cs1_row, bw, row_3_4; in rockchip_sdram_size() local
109 cs0_row = 12; in rockchip_sdram_size()
111 cs0_row = 13 + (sys_reg2 >> in rockchip_sdram_size()
130 cs0_row = 13 + (sys_reg2 >> SYS_REG_CS0_ROW_SHIFT(ch) & in rockchip_sdram_size()
144 chipsize_mb = (1 << (cs0_row + cs0_col + bk + bg + bw - 20)); in rockchip_sdram_size()
147 chipsize_mb += chipsize_mb >> ((cs0_row - cs1_row) + in rockchip_sdram_size()
155 rank, cs0_col, cs1_col, bk, cs0_row, in rockchip_sdram_size()
160 rank, cs0_col, bk, cs0_row, in rockchip_sdram_size()
|
| /dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/arch/arm/mach-rockchip/ |
| H A D | sdram.c | 80 u32 rank, cs0_col, bk, cs0_row, cs1_row, bw, row_3_4; in rockchip_sdram_size() local
109 cs0_row = 12; in rockchip_sdram_size()
111 cs0_row = 13 + (sys_reg2 >> in rockchip_sdram_size()
130 cs0_row = 13 + (sys_reg2 >> SYS_REG_CS0_ROW_SHIFT(ch) & in rockchip_sdram_size()
144 chipsize_mb = (1 << (cs0_row + cs0_col + bk + bg + bw - 20)); in rockchip_sdram_size()
147 chipsize_mb += chipsize_mb >> ((cs0_row - cs1_row) + in rockchip_sdram_size()
155 rank, cs0_col, cs1_col, bk, cs0_row, in rockchip_sdram_size()
160 rank, cs0_col, bk, cs0_row, in rockchip_sdram_size()
|
| /dports/sysutils/u-boot-rpi-0-w/u-boot-2021.07/arch/arm/mach-rockchip/ |
| H A D | sdram.c | 80 u32 rank, cs0_col, bk, cs0_row, cs1_row, bw, row_3_4; in rockchip_sdram_size() local
109 cs0_row = 12; in rockchip_sdram_size()
111 cs0_row = 13 + (sys_reg2 >> in rockchip_sdram_size()
130 cs0_row = 13 + (sys_reg2 >> SYS_REG_CS0_ROW_SHIFT(ch) & in rockchip_sdram_size()
144 chipsize_mb = (1 << (cs0_row + cs0_col + bk + bg + bw - 20)); in rockchip_sdram_size()
147 chipsize_mb += chipsize_mb >> ((cs0_row - cs1_row) + in rockchip_sdram_size()
155 rank, cs0_col, cs1_col, bk, cs0_row, in rockchip_sdram_size()
160 rank, cs0_col, bk, cs0_row, in rockchip_sdram_size()
|
| /dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/arch/arm/mach-rockchip/ |
| H A D | sdram.c | 80 u32 rank, cs0_col, bk, cs0_row, cs1_row, bw, row_3_4; in rockchip_sdram_size() local
109 cs0_row = 12; in rockchip_sdram_size()
111 cs0_row = 13 + (sys_reg2 >> in rockchip_sdram_size()
130 cs0_row = 13 + (sys_reg2 >> SYS_REG_CS0_ROW_SHIFT(ch) & in rockchip_sdram_size()
144 chipsize_mb = (1 << (cs0_row + cs0_col + bk + bg + bw - 20)); in rockchip_sdram_size()
147 chipsize_mb += chipsize_mb >> ((cs0_row - cs1_row) + in rockchip_sdram_size()
155 rank, cs0_col, cs1_col, bk, cs0_row, in rockchip_sdram_size()
160 rank, cs0_col, bk, cs0_row, in rockchip_sdram_size()
|
| /dports/sysutils/u-boot-nanopi-neo/u-boot-2021.07/arch/arm/mach-rockchip/ |
| H A D | sdram.c | 80 u32 rank, cs0_col, bk, cs0_row, cs1_row, bw, row_3_4; in rockchip_sdram_size() local
109 cs0_row = 12; in rockchip_sdram_size()
111 cs0_row = 13 + (sys_reg2 >> in rockchip_sdram_size()
130 cs0_row = 13 + (sys_reg2 >> SYS_REG_CS0_ROW_SHIFT(ch) & in rockchip_sdram_size()
144 chipsize_mb = (1 << (cs0_row + cs0_col + bk + bg + bw - 20)); in rockchip_sdram_size()
147 chipsize_mb += chipsize_mb >> ((cs0_row - cs1_row) + in rockchip_sdram_size()
155 rank, cs0_col, cs1_col, bk, cs0_row, in rockchip_sdram_size()
160 rank, cs0_col, bk, cs0_row, in rockchip_sdram_size()
|
| /dports/sysutils/u-boot-nanopi-a64/u-boot-2021.07/arch/arm/mach-rockchip/ |
| H A D | sdram.c | 80 u32 rank, cs0_col, bk, cs0_row, cs1_row, bw, row_3_4; in rockchip_sdram_size() local
109 cs0_row = 12; in rockchip_sdram_size()
111 cs0_row = 13 + (sys_reg2 >> in rockchip_sdram_size()
130 cs0_row = 13 + (sys_reg2 >> SYS_REG_CS0_ROW_SHIFT(ch) & in rockchip_sdram_size()
144 chipsize_mb = (1 << (cs0_row + cs0_col + bk + bg + bw - 20)); in rockchip_sdram_size()
147 chipsize_mb += chipsize_mb >> ((cs0_row - cs1_row) + in rockchip_sdram_size()
155 rank, cs0_col, cs1_col, bk, cs0_row, in rockchip_sdram_size()
160 rank, cs0_col, bk, cs0_row, in rockchip_sdram_size()
|
| /dports/sysutils/u-boot-nanopi-neo-air/u-boot-2021.07/arch/arm/mach-rockchip/ |
| H A D | sdram.c | 80 u32 rank, cs0_col, bk, cs0_row, cs1_row, bw, row_3_4; in rockchip_sdram_size() local
109 cs0_row = 12; in rockchip_sdram_size()
111 cs0_row = 13 + (sys_reg2 >> in rockchip_sdram_size()
130 cs0_row = 13 + (sys_reg2 >> SYS_REG_CS0_ROW_SHIFT(ch) & in rockchip_sdram_size()
144 chipsize_mb = (1 << (cs0_row + cs0_col + bk + bg + bw - 20)); in rockchip_sdram_size()
147 chipsize_mb += chipsize_mb >> ((cs0_row - cs1_row) + in rockchip_sdram_size()
155 rank, cs0_col, cs1_col, bk, cs0_row, in rockchip_sdram_size()
160 rank, cs0_col, bk, cs0_row, in rockchip_sdram_size()
|
| /dports/sysutils/u-boot-bananapi/u-boot-2021.07/arch/arm/mach-rockchip/ |
| H A D | sdram.c | 80 u32 rank, cs0_col, bk, cs0_row, cs1_row, bw, row_3_4; in rockchip_sdram_size() local
109 cs0_row = 12; in rockchip_sdram_size()
111 cs0_row = 13 + (sys_reg2 >> in rockchip_sdram_size()
130 cs0_row = 13 + (sys_reg2 >> SYS_REG_CS0_ROW_SHIFT(ch) & in rockchip_sdram_size()
144 chipsize_mb = (1 << (cs0_row + cs0_col + bk + bg + bw - 20)); in rockchip_sdram_size()
147 chipsize_mb += chipsize_mb >> ((cs0_row - cs1_row) + in rockchip_sdram_size()
155 rank, cs0_col, cs1_col, bk, cs0_row, in rockchip_sdram_size()
160 rank, cs0_col, bk, cs0_row, in rockchip_sdram_size()
|
| /dports/sysutils/u-boot-wandboard/u-boot-2021.07/arch/arm/mach-rockchip/ |
| H A D | sdram.c | 80 u32 rank, cs0_col, bk, cs0_row, cs1_row, bw, row_3_4; in rockchip_sdram_size() local
109 cs0_row = 12; in rockchip_sdram_size()
111 cs0_row = 13 + (sys_reg2 >> in rockchip_sdram_size()
130 cs0_row = 13 + (sys_reg2 >> SYS_REG_CS0_ROW_SHIFT(ch) & in rockchip_sdram_size()
144 chipsize_mb = (1 << (cs0_row + cs0_col + bk + bg + bw - 20)); in rockchip_sdram_size()
147 chipsize_mb += chipsize_mb >> ((cs0_row - cs1_row) + in rockchip_sdram_size()
155 rank, cs0_col, cs1_col, bk, cs0_row, in rockchip_sdram_size()
160 rank, cs0_col, bk, cs0_row, in rockchip_sdram_size()
|
| /dports/sysutils/u-boot-cubieboard/u-boot-2021.07/arch/arm/mach-rockchip/ |
| H A D | sdram.c | 80 u32 rank, cs0_col, bk, cs0_row, cs1_row, bw, row_3_4; in rockchip_sdram_size() local
109 cs0_row = 12; in rockchip_sdram_size()
111 cs0_row = 13 + (sys_reg2 >> in rockchip_sdram_size()
130 cs0_row = 13 + (sys_reg2 >> SYS_REG_CS0_ROW_SHIFT(ch) & in rockchip_sdram_size()
144 chipsize_mb = (1 << (cs0_row + cs0_col + bk + bg + bw - 20)); in rockchip_sdram_size()
147 chipsize_mb += chipsize_mb >> ((cs0_row - cs1_row) + in rockchip_sdram_size()
155 rank, cs0_col, cs1_col, bk, cs0_row, in rockchip_sdram_size()
160 rank, cs0_col, bk, cs0_row, in rockchip_sdram_size()
|
| /dports/sysutils/u-boot-clearfog/u-boot-2021.07/arch/arm/mach-rockchip/ |
| H A D | sdram.c | 80 u32 rank, cs0_col, bk, cs0_row, cs1_row, bw, row_3_4; in rockchip_sdram_size() local
109 cs0_row = 12; in rockchip_sdram_size()
111 cs0_row = 13 + (sys_reg2 >> in rockchip_sdram_size()
130 cs0_row = 13 + (sys_reg2 >> SYS_REG_CS0_ROW_SHIFT(ch) & in rockchip_sdram_size()
144 chipsize_mb = (1 << (cs0_row + cs0_col + bk + bg + bw - 20)); in rockchip_sdram_size()
147 chipsize_mb += chipsize_mb >> ((cs0_row - cs1_row) + in rockchip_sdram_size()
155 rank, cs0_col, cs1_col, bk, cs0_row, in rockchip_sdram_size()
160 rank, cs0_col, bk, cs0_row, in rockchip_sdram_size()
|
| /dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/arch/arm/mach-rockchip/ |
| H A D | sdram.c | 80 u32 rank, cs0_col, bk, cs0_row, cs1_row, bw, row_3_4; in rockchip_sdram_size() local
109 cs0_row = 12; in rockchip_sdram_size()
111 cs0_row = 13 + (sys_reg2 >> in rockchip_sdram_size()
130 cs0_row = 13 + (sys_reg2 >> SYS_REG_CS0_ROW_SHIFT(ch) & in rockchip_sdram_size()
144 chipsize_mb = (1 << (cs0_row + cs0_col + bk + bg + bw - 20)); in rockchip_sdram_size()
147 chipsize_mb += chipsize_mb >> ((cs0_row - cs1_row) + in rockchip_sdram_size()
155 rank, cs0_col, cs1_col, bk, cs0_row, in rockchip_sdram_size()
160 rank, cs0_col, bk, cs0_row, in rockchip_sdram_size()
|
| /dports/sysutils/u-boot-pandaboard/u-boot-2021.07/arch/arm/mach-rockchip/ |
| H A D | sdram.c | 80 u32 rank, cs0_col, bk, cs0_row, cs1_row, bw, row_3_4; in rockchip_sdram_size() local
109 cs0_row = 12; in rockchip_sdram_size()
111 cs0_row = 13 + (sys_reg2 >> in rockchip_sdram_size()
130 cs0_row = 13 + (sys_reg2 >> SYS_REG_CS0_ROW_SHIFT(ch) & in rockchip_sdram_size()
144 chipsize_mb = (1 << (cs0_row + cs0_col + bk + bg + bw - 20)); in rockchip_sdram_size()
147 chipsize_mb += chipsize_mb >> ((cs0_row - cs1_row) + in rockchip_sdram_size()
155 rank, cs0_col, cs1_col, bk, cs0_row, in rockchip_sdram_size()
160 rank, cs0_col, bk, cs0_row, in rockchip_sdram_size()
|
| /dports/sysutils/u-boot-orangepi-zero/u-boot-2021.07/arch/arm/mach-rockchip/ |
| H A D | sdram.c | 80 u32 rank, cs0_col, bk, cs0_row, cs1_row, bw, row_3_4; in rockchip_sdram_size() local
109 cs0_row = 12; in rockchip_sdram_size()
111 cs0_row = 13 + (sys_reg2 >> in rockchip_sdram_size()
130 cs0_row = 13 + (sys_reg2 >> SYS_REG_CS0_ROW_SHIFT(ch) & in rockchip_sdram_size()
144 chipsize_mb = (1 << (cs0_row + cs0_col + bk + bg + bw - 20)); in rockchip_sdram_size()
147 chipsize_mb += chipsize_mb >> ((cs0_row - cs1_row) + in rockchip_sdram_size()
155 rank, cs0_col, cs1_col, bk, cs0_row, in rockchip_sdram_size()
160 rank, cs0_col, bk, cs0_row, in rockchip_sdram_size()
|
| /dports/sysutils/u-boot-orangepi-r1/u-boot-2021.07/arch/arm/mach-rockchip/ |
| H A D | sdram.c | 80 u32 rank, cs0_col, bk, cs0_row, cs1_row, bw, row_3_4; in rockchip_sdram_size() local
109 cs0_row = 12; in rockchip_sdram_size()
111 cs0_row = 13 + (sys_reg2 >> in rockchip_sdram_size()
130 cs0_row = 13 + (sys_reg2 >> SYS_REG_CS0_ROW_SHIFT(ch) & in rockchip_sdram_size()
144 chipsize_mb = (1 << (cs0_row + cs0_col + bk + bg + bw - 20)); in rockchip_sdram_size()
147 chipsize_mb += chipsize_mb >> ((cs0_row - cs1_row) + in rockchip_sdram_size()
155 rank, cs0_col, cs1_col, bk, cs0_row, in rockchip_sdram_size()
160 rank, cs0_col, bk, cs0_row, in rockchip_sdram_size()
|
| /dports/sysutils/u-boot-orangepi-zero-plus/u-boot-2021.07/arch/arm/mach-rockchip/ |
| H A D | sdram.c | 80 u32 rank, cs0_col, bk, cs0_row, cs1_row, bw, row_3_4; in rockchip_sdram_size() local
109 cs0_row = 12; in rockchip_sdram_size()
111 cs0_row = 13 + (sys_reg2 >> in rockchip_sdram_size()
130 cs0_row = 13 + (sys_reg2 >> SYS_REG_CS0_ROW_SHIFT(ch) & in rockchip_sdram_size()
144 chipsize_mb = (1 << (cs0_row + cs0_col + bk + bg + bw - 20)); in rockchip_sdram_size()
147 chipsize_mb += chipsize_mb >> ((cs0_row - cs1_row) + in rockchip_sdram_size()
155 rank, cs0_col, cs1_col, bk, cs0_row, in rockchip_sdram_size()
160 rank, cs0_col, bk, cs0_row, in rockchip_sdram_size()
|