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Searched refs:ctrl_tx_enable_ctx (Results 1 – 4 of 4) sorted by relevance

/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/xge/rtl/verilog/
H A Dsync_clk_xgmii_tx.v43 ctrl_tx_enable_ctx, status_local_fault_ctx, status_remote_fault_ctx,
57 output ctrl_tx_enable_ctx; port
68 assign ctrl_tx_enable_ctx = sig_out[2];
H A Dxge_mac.v100 wire ctrl_tx_enable_ctx; // From sync_clk_xgmii_tx0 of sync_clk_xgmii_tx.v net
252 .ctrl_tx_enable_ctx (ctrl_tx_enable_ctx),
312 .ctrl_tx_enable_ctx(ctrl_tx_enable_ctx),
H A Dtx_dequeue.v46 clk_xgmii_tx, reset_xgmii_tx_n, ctrl_tx_enable_ctx,
59 input ctrl_tx_enable_ctx; port
297 always @(/*AS*/crc32_tx or ctrl_tx_enable_ctx or curr_state_enc or eop
332 if (ctrl_tx_enable_ctx && frame_available &&
H A Dxge_mac_wb.v101 wire ctrl_tx_enable_ctx; // From sync_clk_xgmii_tx0 of sync_clk_xgmii_tx.v net