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Searched refs:ctrlport_resp_ack (Results 1 – 23 of 23) sorted by relevance

/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_vector_iir/
H A Drfnoc_block_vector_iir.v275 reg ctrlport_resp_ack; register
283 assign dec_ctrlport_resp_ack[port] = ctrlport_resp_ack;
324 ctrlport_resp_ack <= 1'b0;
333 ctrlport_resp_ack <= 1;
350 ctrlport_resp_ack <= 1;
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_siggen/
H A Drfnoc_block_siggen.v179 wire [ 1*NUM_PORTS-1:0] ctrlport_resp_ack; net
206 .m_ctrlport_resp_ack (ctrlport_resp_ack),
227 .s_ctrlport_resp_ack (ctrlport_resp_ack [port* 1 +: 1]),
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_null_src_sink/
H A Drfnoc_block_null_src_sink.v88 reg ctrlport_resp_ack; register
140 .m_ctrlport_resp_ack (ctrlport_resp_ack),
293 ctrlport_resp_ack <= 1'b0;
296 ctrlport_resp_ack <= ctrlport_req_wr | ctrlport_req_rd;
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_moving_avg/
H A Drfnoc_block_moving_avg.v215 wire [ 1*NUM_PORTS-1:0] ctrlport_resp_ack; net
242 .m_ctrlport_resp_ack (ctrlport_resp_ack),
263 .s_ctrlport_resp_ack (ctrlport_resp_ack [port* 1 +: 1]),
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_window/
H A Drfnoc_block_window.v218 wire [ 1*NUM_PORTS-1:0] ctrlport_resp_ack; net
245 .m_ctrlport_resp_ack (ctrlport_resp_ack),
268 .s_ctrlport_resp_ack (ctrlport_resp_ack [port* 1 +: 1]),
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/core/
H A Drfnoc_core_kernel.v153 reg ctrlport_resp_ack; register
183 .m_ctrlport_resp_ack (ctrlport_resp_ack ),
234 ctrlport_resp_ack <= blk_resp_ack | con_resp_ack;
H A Dchdr_stream_endpoint.v184 reg ctrlport_resp_ack = 1'b0; register
206 .ctrlport_resp_ack(ctrlport_resp_ack), .ctrlport_resp_data(ctrlport_resp_data),
301 ctrlport_resp_ack <= 1'b0;
304 ctrlport_resp_ack <= ctrlport_req_wr | ctrlport_req_rd;
H A Daxis_ctrl_master.v53 output wire ctrlport_resp_ack, port
310 assign ctrlport_resp_ack = (state == ST_RESP_OP_DATA && s_axis_ctrl_tvalid) ||
H A Dchdr_mgmt_pkt_handler.v59 input wire ctrlport_resp_ack, port
356 if (ctrlport_resp_ack) begin
599 ((pkt_state == ST_MGMT_OP_WAIT) && (op_code == CHDR_MGMT_OP_CFG_RD_REQ) && ctrlport_resp_ack) ||
H A Daxis_ctrl_slave.v46 input wire ctrlport_resp_ack, port
235 if (ctrlport_resp_ack) begin
H A Dctrlport_endpoint.v231 .ctrlport_resp_ack (s_ctrlport_resp_ack),
270 .ctrlport_resp_ack (m_ctrlport_resp_ack),
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_replay/
H A Drfnoc_block_replay.v150 wire ctrlport_resp_ack; net
230 .m_ctrlport_resp_ack (ctrlport_resp_ack),
295 .s_ctrlport_resp_ack (ctrlport_resp_ack),
315 assign ctrlport_resp_ack = dec_ctrlport_resp_ack;
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/host/utils/rfnoc_blocktool/templates/modules/
H A Dctrlport_wires_template.mako29 ${sl_wire}wire ${ma_pre}ctrlport_resp_ack${term}
52 ${ma_wire}wire ${sl_pre}ctrlport_resp_ack${term}
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_duc/
H A Drfnoc_block_duc.v93 wire ctrlport_resp_ack; net
160 .m_ctrlport_resp_ack (ctrlport_resp_ack),
214 .s_ctrlport_resp_ack (ctrlport_resp_ack),
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/xport/
H A Dchdr_xport_adapter_generic.v78 input wire ctrlport_resp_ack, port
166 .ctrlport_resp_ack(ctrlport_resp_ack), .ctrlport_resp_data(ctrlport_resp_data),
H A Deth_ipv4_chdr64_adapter.v192 .ctrlport_resp_ack (/* unused */),
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_ddc/
H A Drfnoc_block_ddc.v93 wire ctrlport_resp_ack; net
160 .m_ctrlport_resp_ack (ctrlport_resp_ack),
215 .s_ctrlport_resp_ack (ctrlport_resp_ack),
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_axi_ram_fifo/
H A Drfnoc_block_axi_ram_fifo.v216 wire ctrlport_resp_ack; net
268 .m_ctrlport_resp_ack (ctrlport_resp_ack),
315 .s_ctrlport_resp_ack (ctrlport_resp_ack),
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/top/x300/
H A Dnirio_chdr64_adapter.v106 .ctrlport_resp_ack (/* unused */ 1'b0),
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/blocks/rfnoc_block_fft/
H A Drfnoc_block_fft.v89 wire ctrlport_resp_ack; net
156 .m_ctrlport_resp_ack (ctrlport_resp_ack ),
209 .s_ctrlport_resp_ack (ctrlport_resp_ack),
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/host/include/uhd/rfnoc/core/
H A Dio_signatures.yml22 - name: ctrlport_resp_ack
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/crossbar/
H A Dchdr_crossbar_nxn.v201 .ctrlport_resp_ack (rtcfg_resp_ack[n] ),
/dports/comms/uhd/uhd-90ce6062b6b5df2eddeee723777be85108e4e7c7/fpga/usrp3/lib/rfnoc/xport_sv/
H A Dchdr_xport_adapter.sv196 .ctrlport_resp_ack (1'b0 /* unused */),