| /dports/cad/verilator/verilator-4.216/test_regress/t/ |
| H A D | t_var_escape.v | 16 integer cyc; initial cyc=1; register
26 wire \9num = cyc[0];
30 wire \wire = cyc[0];
32 wire \check_alias = cyc[0];
33 wire \check:alias = cyc[0];
34 wire \check;alias = !cyc[0];
40 sub a0 (.cyc(cyc));
42 sub \mod.with_dot (.cyc(cyc));
45 cyc <= cyc + 1;
57 if (cyc==10) begin
[all …]
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| H A D | t_assert_cover.v | 14 integer cyc; initial cyc=1; register
20 .cyc (cyc[31:0]));
26 if (cyc!=0) begin
27 cyc <= cyc + 1;
28 toggle <= !cyc[0];
29 if (cyc==9) begin
31 if (cyc==10) begin
44 input [31:0] cyc port
72 labeled_icov: cover (cyc==3 || cyc==4);
103 cyc==5;
[all …]
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| H A D | t_assert_implication.v | 13 integer cyc; initial cyc=1; register
18 .cyc(cyc));
21 if (cyc!=0) begin
22 cyc <= cyc + 1;
38 input integer cyc port
54 cyc%3==1 |=> cyc%3==1
59 cyc%3==1 |=> cyc%3==0
64 (cyc == 4) |=> 0
69 (cyc == 4) |=> 0
109 cyc%3==1 |=> cyc%3==2
[all …]
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| H A D | t_uniqueif.v | 14 integer cyc=1; register
18 cyc <= cyc + 1;
25 unique0 if (cyc > 5)
29 unique0 if (cyc < 3)
37 else if (cyc > 3)
43 else if (cyc > 3)
49 unique if (cyc < 3)
57 else if (cyc >= 3)
63 else if (cyc > 3)
76 else if (cyc < 5)
[all …]
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| H A D | t_math_shortreal.v | 21 integer cyc = 0; register
91 cyc <= cyc + 1;
92 if (cyc==0) begin
95 else if (cyc<90) begin
97 if ($itor(cyc) != cyc) $stop;
99 r = $itor(cyc*2);
101 if (i!=cyc*2) $stop;
103 r = $itor(cyc)/1.5;
109 r = $itor(cyc);
118 r2 = $itor(cyc);
[all …]
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| H A D | t_sys_fstrobe.v | 16 int cyc = 0; register
21 cyc <= cyc + 1;
22 if (cyc == 5) begin
25 else if (cyc == 10) begin
29 else if (cyc == 17) begin
32 else if (cyc == 18) begin
35 else if (cyc == 19) begin
38 else if (cyc == 22) begin
41 else if (cyc == 24) begin
44 else if (cyc == 26) begin
[all …]
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| H A D | t_sys_fmonitor.v | 16 int cyc = 0; register
21 cyc <= cyc + 1;
22 if (cyc == 5) begin
25 else if (cyc == 10) begin
29 else if (cyc == 17) begin
32 else if (cyc == 18) begin
35 else if (cyc == 19) begin
38 else if (cyc == 22) begin
41 else if (cyc == 24) begin
46 else if (cyc == 26) begin
[all …]
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| H A D | t_assert_property.v | 13 integer cyc; initial cyc=1; register
18 .cyc (cyc[31:0]));
21 if (cyc!=0) begin
22 cyc <= cyc + 1;
23 if (cyc==10) begin
35 input [31:0] cyc port
39 assert property (@(posedge clk) cyc==3)
41 assume property (@(posedge clk) cyc==3)
46 assert property (@(posedge clk) cyc!=3);
47 assume property (@(posedge clk) cyc!=3);
[all …]
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| H A D | t_sys_strobe.v | 14 int cyc = 0; register
18 cyc <= cyc + 1;
19 if (cyc == 10) begin
23 else if (cyc == 17) begin
24 $strobeb(cyc, "b");
26 else if (cyc == 18) begin
27 $strobeh(cyc, "h");
29 else if (cyc == 19) begin
30 $strobeo(cyc, "o");
32 else if (cyc == 22) begin
[all …]
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| H A D | t_math_real.v | 31 integer cyc = 0; register
144 cyc <= cyc + 1;
145 if (cyc==0) begin
158 else if (cyc<80) begin
160 if ($itor(cyc) != cyc) $stop;
162 r = $itor(cyc*2);
164 if (i!=cyc*2) $stop;
166 r = $itor(cyc)/1.5;
172 r = $itor(cyc);
181 r2 = $itor(cyc);
[all …]
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| H A D | t_math_reverse.v | 13 integer cyc; initial cyc=1; register
55 if (cyc!=0) begin
56 cyc<=cyc+1;
59 if (cyc==1) begin
62 if (cyc==2 && bitrev!=8'hb7) $stop;
63 if (cyc==3 && bitrev!=8'h5b) $stop;
64 if (cyc==4 && bitrev!=8'h2d) $stop;
65 if (cyc==5 && bitrev!=8'h16) $stop;
66 if (cyc==6 && bitrev!=8'h8b) $stop;
67 if (cyc==7 && bitrev!=8'hc5) $stop;
[all …]
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| H A D | t_sys_monitor.v | 14 int cyc = 0; register
18 cyc <= cyc + 1;
19 if (cyc == 10) begin
22 else if (cyc == 17) begin
23 $monitorb(cyc, "b");
25 else if (cyc == 18) begin
26 $monitorh(cyc, "h");
28 else if (cyc == 19) begin
29 $monitoro(cyc, "o");
31 else if (cyc == 22) begin
[all …]
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| H A D | t_cover_sva_notflat.v | 14 integer cyc; initial cyc=1; register
20 .cyc (cyc[31:0]));
25 .cyc (cyc[31:0]));
30 .cyc (cyc[31:0]));
33 if (cyc!=0) begin
34 cyc <= cyc + 1;
35 toggle <= !cyc[0];
36 if (cyc==9) begin
38 if (cyc==10) begin
51 input [31:0] cyc port
[all …]
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| H A D | t_tri_pull01.v | 13 integer cyc = 0; register
19 bufif1 (t, crc[1], cyc[1:0]==2'b00);
20 bufif1 (t, crc[2], cyc[1:0]==2'b10);
23 bufif1 (t0, crc[1], cyc[1:0]==2'b00);
24 bufif1 (t0, crc[2], cyc[1:0]==2'b10);
27 bufif1 (t1, crc[1], cyc[1:0]==2'b00);
45 cyc <= cyc + 1;
48 if (cyc==0) begin
53 else if (cyc<10) begin
56 else if (cyc<90) begin
[all …]
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| H A D | t_assert_basic.v | 16 integer cyc; initial cyc=1; register
17 wire [7:0] cyc_copy = cyc[7:0];
20 AssertionFalse1: assert (cyc<100);
21 assert (!(cyc==5) || toggle);
28 if (cyc!=0) begin
29 cyc <= cyc + 1;
30 toggle <= !cyc[0];
31 if (cyc==7) assert (cyc[0] == cyc[1]); // bug743
32 if (cyc==9) begin
37 assert (0) else $info("Info message, cyc=%d", cyc);
[all …]
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| H A D | t_math_vgen.v | 13 integer cyc; initial cyc=1; register
23 if (cyc==1) begin
29 if (cyc==2) begin
38 if (cyc==1) begin
43 if (cyc==2) begin
54 if (cyc==1) begin
59 if (cyc==2) begin
71 if (cyc==1) begin
298 cyc <= cyc + 1;
299 if (cyc==18) begin
[all …]
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| /dports/cad/gmsh/gmsh-4.9.2-source/contrib/blossom/concorde97/LINKERN/ |
| H A D | flip_ll5.c | 97 int *cyc;
108 lltour[cyc[0]].actual_fwd.name = cyc[0];
114 lltour[cyc[0]].fwd = &(lltour[cyc[0]].actual_fwd);
115 lltour[cyc[0]].actual_bwd.name = cyc[0];
121 lltour[cyc[0]].bwd = &(lltour[cyc[0]].actual_bwd);
122 lltour[cyc[ncount - 1]].actual_fwd.name = cyc[ncount - 1];
129 lltour[cyc[ncount - 1]].actual_bwd.name = cyc[ncount - 1];
140 lltour[cyc[i]].actual_fwd.name = cyc[i];
146 lltour[cyc[i]].fwd = &(lltour[cyc[i]].actual_fwd);
147 lltour[cyc[i]].actual_bwd.name = cyc[i];
[all …]
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| H A D | flip_llD.c | 124 int *cyc;
137 lltour[cyc[0]].actual_fwd.name = cyc[0];
142 lltour[cyc[0]].actual_bwd.name = cyc[0];
161 lltour[cyc[i]].actual_fwd.name = cyc[i];
166 lltour[cyc[i]].actual_bwd.name = cyc[i];
238 lltour[cyc[0]].actual_fwd_super.name = cyc[0];
239 lltour[cyc[0]].actual_bwd_super.name = cyc[0];
273 lltour[cyc[i]].actual_fwd_super.name = cyc[i];
274 lltour[cyc[i]].actual_bwd_super.name = cyc[i];
312 lltour[cyc[i]].next_auto = &(lltour[cyc[0]]);
[all …]
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| H A D | flip_ll8.c | 110 int *cyc;
123 lltour[cyc[0]].actual_fwd.name = cyc[0];
128 lltour[cyc[0]].actual_bwd.name = cyc[0];
147 lltour[cyc[i]].actual_fwd.name = cyc[i];
152 lltour[cyc[i]].actual_bwd.name = cyc[i];
169 lltour[cyc[0]].actual_fwd_express.name = cyc[0];
170 lltour[cyc[0]].actual_bwd_express.name = cyc[0];
201 lltour[cyc[i]].actual_fwd_express.name = cyc[i];
202 lltour[cyc[i]].actual_bwd_express.name = cyc[i];
230 lltour[cyc[i]].next_super = &(lltour[cyc[0]]);
[all …]
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| H A D | flip_ll6.c | 103 int *cyc;
115 lltour[cyc[0]].actual_fwd.name = cyc[0];
120 lltour[cyc[0]].fwd = &(lltour[cyc[0]].actual_fwd);
121 lltour[cyc[0]].actual_bwd.name = cyc[0];
126 lltour[cyc[0]].bwd = &(lltour[cyc[0]].actual_bwd);
143 lltour[cyc[i]].actual_fwd.name = cyc[i];
148 lltour[cyc[i]].fwd = &(lltour[cyc[i]].actual_fwd);
149 lltour[cyc[i]].actual_bwd.name = cyc[i];
154 lltour[cyc[i]].bwd = &(lltour[cyc[i]].actual_bwd);
172 lltour[cyc[i]].next_express = &(lltour[cyc[0]]);
[all …]
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| H A D | flip_llC.c | 115 int *cyc;
128 lltour[cyc[0]].actual_fwd.name = cyc[0];
133 lltour[cyc[0]].actual_bwd.name = cyc[0];
152 lltour[cyc[i]].actual_fwd.name = cyc[i];
157 lltour[cyc[i]].actual_bwd.name = cyc[i];
174 lltour[cyc[0]].actual_fwd_express.name = cyc[0];
175 lltour[cyc[0]].actual_bwd_express.name = cyc[0];
207 lltour[cyc[i]].actual_fwd_express.name = cyc[i];
208 lltour[cyc[i]].actual_bwd_express.name = cyc[i];
238 lltour[cyc[i]].next_super = &(lltour[cyc[0]]);
[all …]
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| H A D | flip_llB.c | 106 int *cyc;
119 lltour[cyc[0]].actual_fwd.name = cyc[0];
124 lltour[cyc[0]].fwd = &(lltour[cyc[0]].actual_fwd);
125 lltour[cyc[0]].actual_bwd.name = cyc[0];
130 lltour[cyc[0]].bwd = &(lltour[cyc[0]].actual_bwd);
147 lltour[cyc[i]].actual_fwd.name = cyc[i];
152 lltour[cyc[i]].fwd = &(lltour[cyc[i]].actual_fwd);
153 lltour[cyc[i]].actual_bwd.name = cyc[i];
158 lltour[cyc[i]].bwd = &(lltour[cyc[i]].actual_bwd);
182 lltour[cyc[i]].next_express = &(lltour[cyc[0]]);
[all …]
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| H A D | flip_ll7.c | 101 int *cyc;
114 lltour[cyc[0]].actual_fwd.name = cyc[0];
119 lltour[cyc[0]].fwd = &(lltour[cyc[0]].actual_fwd);
120 lltour[cyc[0]].actual_bwd.name = cyc[0];
125 lltour[cyc[0]].bwd = &(lltour[cyc[0]].actual_bwd);
142 lltour[cyc[i]].actual_fwd.name = cyc[i];
147 lltour[cyc[i]].fwd = &(lltour[cyc[i]].actual_fwd);
148 lltour[cyc[i]].actual_bwd.name = cyc[i];
153 lltour[cyc[i]].bwd = &(lltour[cyc[i]].actual_bwd);
173 lltour[cyc[i]].next_express = &(lltour[cyc[0]]);
[all …]
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| H A D | flip_try.c | 149 int *cyc;
168 lltour[cyc[0]].actual_fwd.name = cyc[0];
173 lltour[cyc[0]].actual_bwd.name = cyc[0];
192 lltour[cyc[i]].actual_fwd.name = cyc[i];
197 lltour[cyc[i]].actual_bwd.name = cyc[i];
216 lltour[cyc[0]].actual_fwd_express.name = cyc[0];
217 lltour[cyc[0]].actual_bwd_express.name = cyc[0];
248 lltour[cyc[i]].actual_fwd_express.name = cyc[i];
277 lltour[cyc[i]].next_super = &(lltour[cyc[0]]);
279 lltour[cyc[0]].prev_super = &(lltour[cyc[i]]);
[all …]
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| /dports/math/SCIP/scip-7.0.3/applications/CycleClustering/check/testset/ |
| H A D | hard.test | 1 ../instances/Pot/3Cycle/Pot3Cycle_20B_sym.txt_3cluster.cyc
2 ../instances/Pot/3Cycle/Pot3Cycle_30B_sym.txt_3cluster.cyc
3 ../instances/Pot/3Cycle/Pot3_T_20.txt_3cluster.cyc
4 ../instances/Pot/3Cycle/Pot3_T_50.txt_3cluster.cyc
5 ../instances/Pot/3Cycle/Pot3_T_100.txt_3cluster.cyc
8 ../instances/Pot/4Cycle/Pot4_T_50.txt_4cluster.cyc
9 ../instances/Pot/4Cycle/Pot4_T_100.txt_4cluster.cyc
10 ../instances/Pot/4Cycle/Pot4_T_20.txt_4cluster.cyc
11 ../instances/Pot/6Cycle/Pot6_T_20.txt_6cluster.cyc
12 ../instances/Pot/6Cycle/Pot6_T_50.txt_6cluster.cyc
[all …]
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