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Searched refs:ddr_timing (Results 1 – 25 of 132) sorted by relevance

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/dports/emulators/qemu5/qemu-5.2.0/roms/u-boot/arch/arm/mach-rockchip/rk3036/
H A Dsdram_rk3036.c43 const struct rk3036_ddr_timing ddr_timing = {0x18c, variable
401 if (freq < ddr_timing.freq) { in phy_dll_bypass_set()
461 (ddr_timing.phy_timing.mr[2] & CMD_ADDR_MASK) << in memory_init()
466 (ddr_timing.phy_timing.mr[3] & CMD_ADDR_MASK) << in memory_init()
471 (ddr_timing.phy_timing.mr[1] & CMD_ADDR_MASK) << in memory_init()
476 (ddr_timing.phy_timing.mr[0] & CMD_ADDR_MASK) << in memory_init()
603 if ((ddr_timing.noc_timing.burstlen << 1) == 4) in pctl_cfg()
608 copy_to_reg(&pctl->togcnt1u, &ddr_timing.pctl_timing.togcnt1u, in pctl_cfg()
629 writel(ddr_timing.noc_timing.noc_timing, &axi_bus->ddrtiming); in phy_cfg()
636 writel(ddr_timing.phy_timing.cl_al, &ddr_phy->ddrphy_reg4a); in phy_cfg()
[all …]
/dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/arch/arm/mach-rockchip/rk3036/
H A Dsdram_rk3036.c44 const struct rk3036_ddr_timing ddr_timing = {0x18c, variable
402 if (freq < ddr_timing.freq) { in phy_dll_bypass_set()
462 (ddr_timing.phy_timing.mr[2] & CMD_ADDR_MASK) << in memory_init()
467 (ddr_timing.phy_timing.mr[3] & CMD_ADDR_MASK) << in memory_init()
472 (ddr_timing.phy_timing.mr[1] & CMD_ADDR_MASK) << in memory_init()
477 (ddr_timing.phy_timing.mr[0] & CMD_ADDR_MASK) << in memory_init()
604 if ((ddr_timing.noc_timing.burstlen << 1) == 4) in pctl_cfg()
609 copy_to_reg(&pctl->togcnt1u, &ddr_timing.pctl_timing.togcnt1u, in pctl_cfg()
630 writel(ddr_timing.noc_timing.noc_timing, &axi_bus->ddrtiming); in phy_cfg()
637 writel(ddr_timing.phy_timing.cl_al, &ddr_phy->ddrphy_reg4a); in phy_cfg()
[all …]
/dports/sysutils/u-boot-olinuxino-lime2-emmc/u-boot-2021.07/arch/arm/mach-rockchip/rk3036/
H A Dsdram_rk3036.c44 const struct rk3036_ddr_timing ddr_timing = {0x18c, variable
402 if (freq < ddr_timing.freq) { in phy_dll_bypass_set()
462 (ddr_timing.phy_timing.mr[2] & CMD_ADDR_MASK) << in memory_init()
467 (ddr_timing.phy_timing.mr[3] & CMD_ADDR_MASK) << in memory_init()
472 (ddr_timing.phy_timing.mr[1] & CMD_ADDR_MASK) << in memory_init()
477 (ddr_timing.phy_timing.mr[0] & CMD_ADDR_MASK) << in memory_init()
604 if ((ddr_timing.noc_timing.burstlen << 1) == 4) in pctl_cfg()
609 copy_to_reg(&pctl->togcnt1u, &ddr_timing.pctl_timing.togcnt1u, in pctl_cfg()
630 writel(ddr_timing.noc_timing.noc_timing, &axi_bus->ddrtiming); in phy_cfg()
637 writel(ddr_timing.phy_timing.cl_al, &ddr_phy->ddrphy_reg4a); in phy_cfg()
[all …]
/dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/arch/arm/mach-rockchip/rk3036/
H A Dsdram_rk3036.c44 const struct rk3036_ddr_timing ddr_timing = {0x18c, variable
402 if (freq < ddr_timing.freq) { in phy_dll_bypass_set()
462 (ddr_timing.phy_timing.mr[2] & CMD_ADDR_MASK) << in memory_init()
467 (ddr_timing.phy_timing.mr[3] & CMD_ADDR_MASK) << in memory_init()
472 (ddr_timing.phy_timing.mr[1] & CMD_ADDR_MASK) << in memory_init()
477 (ddr_timing.phy_timing.mr[0] & CMD_ADDR_MASK) << in memory_init()
604 if ((ddr_timing.noc_timing.burstlen << 1) == 4) in pctl_cfg()
609 copy_to_reg(&pctl->togcnt1u, &ddr_timing.pctl_timing.togcnt1u, in pctl_cfg()
630 writel(ddr_timing.noc_timing.noc_timing, &axi_bus->ddrtiming); in phy_cfg()
637 writel(ddr_timing.phy_timing.cl_al, &ddr_phy->ddrphy_reg4a); in phy_cfg()
[all …]
/dports/sysutils/u-boot-chip/u-boot-2021.07/arch/arm/mach-rockchip/rk3036/
H A Dsdram_rk3036.c44 const struct rk3036_ddr_timing ddr_timing = {0x18c, variable
402 if (freq < ddr_timing.freq) { in phy_dll_bypass_set()
462 (ddr_timing.phy_timing.mr[2] & CMD_ADDR_MASK) << in memory_init()
467 (ddr_timing.phy_timing.mr[3] & CMD_ADDR_MASK) << in memory_init()
472 (ddr_timing.phy_timing.mr[1] & CMD_ADDR_MASK) << in memory_init()
477 (ddr_timing.phy_timing.mr[0] & CMD_ADDR_MASK) << in memory_init()
604 if ((ddr_timing.noc_timing.burstlen << 1) == 4) in pctl_cfg()
609 copy_to_reg(&pctl->togcnt1u, &ddr_timing.pctl_timing.togcnt1u, in pctl_cfg()
630 writel(ddr_timing.noc_timing.noc_timing, &axi_bus->ddrtiming); in phy_cfg()
637 writel(ddr_timing.phy_timing.cl_al, &ddr_phy->ddrphy_reg4a); in phy_cfg()
[all …]
/dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/arch/arm/mach-rockchip/rk3036/
H A Dsdram_rk3036.c44 const struct rk3036_ddr_timing ddr_timing = {0x18c, variable
402 if (freq < ddr_timing.freq) { in phy_dll_bypass_set()
462 (ddr_timing.phy_timing.mr[2] & CMD_ADDR_MASK) << in memory_init()
467 (ddr_timing.phy_timing.mr[3] & CMD_ADDR_MASK) << in memory_init()
472 (ddr_timing.phy_timing.mr[1] & CMD_ADDR_MASK) << in memory_init()
477 (ddr_timing.phy_timing.mr[0] & CMD_ADDR_MASK) << in memory_init()
604 if ((ddr_timing.noc_timing.burstlen << 1) == 4) in pctl_cfg()
609 copy_to_reg(&pctl->togcnt1u, &ddr_timing.pctl_timing.togcnt1u, in pctl_cfg()
630 writel(ddr_timing.noc_timing.noc_timing, &axi_bus->ddrtiming); in phy_cfg()
637 writel(ddr_timing.phy_timing.cl_al, &ddr_phy->ddrphy_reg4a); in phy_cfg()
[all …]
/dports/sysutils/u-boot-sinovoip-bpi-m3/u-boot-2021.07/arch/arm/mach-rockchip/rk3036/
H A Dsdram_rk3036.c44 const struct rk3036_ddr_timing ddr_timing = {0x18c, variable
402 if (freq < ddr_timing.freq) { in phy_dll_bypass_set()
462 (ddr_timing.phy_timing.mr[2] & CMD_ADDR_MASK) << in memory_init()
467 (ddr_timing.phy_timing.mr[3] & CMD_ADDR_MASK) << in memory_init()
472 (ddr_timing.phy_timing.mr[1] & CMD_ADDR_MASK) << in memory_init()
477 (ddr_timing.phy_timing.mr[0] & CMD_ADDR_MASK) << in memory_init()
604 if ((ddr_timing.noc_timing.burstlen << 1) == 4) in pctl_cfg()
609 copy_to_reg(&pctl->togcnt1u, &ddr_timing.pctl_timing.togcnt1u, in pctl_cfg()
630 writel(ddr_timing.noc_timing.noc_timing, &axi_bus->ddrtiming); in phy_cfg()
637 writel(ddr_timing.phy_timing.cl_al, &ddr_phy->ddrphy_reg4a); in phy_cfg()
[all …]
/dports/sysutils/u-boot-a13-olinuxino/u-boot-2021.07/arch/arm/mach-rockchip/rk3036/
H A Dsdram_rk3036.c44 const struct rk3036_ddr_timing ddr_timing = {0x18c, variable
402 if (freq < ddr_timing.freq) { in phy_dll_bypass_set()
462 (ddr_timing.phy_timing.mr[2] & CMD_ADDR_MASK) << in memory_init()
467 (ddr_timing.phy_timing.mr[3] & CMD_ADDR_MASK) << in memory_init()
472 (ddr_timing.phy_timing.mr[1] & CMD_ADDR_MASK) << in memory_init()
477 (ddr_timing.phy_timing.mr[0] & CMD_ADDR_MASK) << in memory_init()
604 if ((ddr_timing.noc_timing.burstlen << 1) == 4) in pctl_cfg()
609 copy_to_reg(&pctl->togcnt1u, &ddr_timing.pctl_timing.togcnt1u, in pctl_cfg()
630 writel(ddr_timing.noc_timing.noc_timing, &axi_bus->ddrtiming); in phy_cfg()
637 writel(ddr_timing.phy_timing.cl_al, &ddr_phy->ddrphy_reg4a); in phy_cfg()
[all …]
/dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/arch/arm/mach-rockchip/rk3036/
H A Dsdram_rk3036.c44 const struct rk3036_ddr_timing ddr_timing = {0x18c, variable
402 if (freq < ddr_timing.freq) { in phy_dll_bypass_set()
462 (ddr_timing.phy_timing.mr[2] & CMD_ADDR_MASK) << in memory_init()
467 (ddr_timing.phy_timing.mr[3] & CMD_ADDR_MASK) << in memory_init()
472 (ddr_timing.phy_timing.mr[1] & CMD_ADDR_MASK) << in memory_init()
477 (ddr_timing.phy_timing.mr[0] & CMD_ADDR_MASK) << in memory_init()
604 if ((ddr_timing.noc_timing.burstlen << 1) == 4) in pctl_cfg()
609 copy_to_reg(&pctl->togcnt1u, &ddr_timing.pctl_timing.togcnt1u, in pctl_cfg()
630 writel(ddr_timing.noc_timing.noc_timing, &axi_bus->ddrtiming); in phy_cfg()
637 writel(ddr_timing.phy_timing.cl_al, &ddr_phy->ddrphy_reg4a); in phy_cfg()
[all …]
/dports/sysutils/u-boot-sopine-spi/u-boot-2021.07/arch/arm/mach-rockchip/rk3036/
H A Dsdram_rk3036.c44 const struct rk3036_ddr_timing ddr_timing = {0x18c, variable
402 if (freq < ddr_timing.freq) { in phy_dll_bypass_set()
462 (ddr_timing.phy_timing.mr[2] & CMD_ADDR_MASK) << in memory_init()
467 (ddr_timing.phy_timing.mr[3] & CMD_ADDR_MASK) << in memory_init()
472 (ddr_timing.phy_timing.mr[1] & CMD_ADDR_MASK) << in memory_init()
477 (ddr_timing.phy_timing.mr[0] & CMD_ADDR_MASK) << in memory_init()
604 if ((ddr_timing.noc_timing.burstlen << 1) == 4) in pctl_cfg()
609 copy_to_reg(&pctl->togcnt1u, &ddr_timing.pctl_timing.togcnt1u, in pctl_cfg()
630 writel(ddr_timing.noc_timing.noc_timing, &axi_bus->ddrtiming); in phy_cfg()
637 writel(ddr_timing.phy_timing.cl_al, &ddr_phy->ddrphy_reg4a); in phy_cfg()
[all …]
/dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/arch/arm/mach-rockchip/rk3036/
H A Dsdram_rk3036.c44 const struct rk3036_ddr_timing ddr_timing = {0x18c, variable
402 if (freq < ddr_timing.freq) { in phy_dll_bypass_set()
462 (ddr_timing.phy_timing.mr[2] & CMD_ADDR_MASK) << in memory_init()
467 (ddr_timing.phy_timing.mr[3] & CMD_ADDR_MASK) << in memory_init()
472 (ddr_timing.phy_timing.mr[1] & CMD_ADDR_MASK) << in memory_init()
477 (ddr_timing.phy_timing.mr[0] & CMD_ADDR_MASK) << in memory_init()
604 if ((ddr_timing.noc_timing.burstlen << 1) == 4) in pctl_cfg()
609 copy_to_reg(&pctl->togcnt1u, &ddr_timing.pctl_timing.togcnt1u, in pctl_cfg()
630 writel(ddr_timing.noc_timing.noc_timing, &axi_bus->ddrtiming); in phy_cfg()
637 writel(ddr_timing.phy_timing.cl_al, &ddr_phy->ddrphy_reg4a); in phy_cfg()
[all …]
/dports/sysutils/u-boot-rpi-0-w/u-boot-2021.07/arch/arm/mach-rockchip/rk3036/
H A Dsdram_rk3036.c44 const struct rk3036_ddr_timing ddr_timing = {0x18c, variable
402 if (freq < ddr_timing.freq) { in phy_dll_bypass_set()
462 (ddr_timing.phy_timing.mr[2] & CMD_ADDR_MASK) << in memory_init()
467 (ddr_timing.phy_timing.mr[3] & CMD_ADDR_MASK) << in memory_init()
472 (ddr_timing.phy_timing.mr[1] & CMD_ADDR_MASK) << in memory_init()
477 (ddr_timing.phy_timing.mr[0] & CMD_ADDR_MASK) << in memory_init()
604 if ((ddr_timing.noc_timing.burstlen << 1) == 4) in pctl_cfg()
609 copy_to_reg(&pctl->togcnt1u, &ddr_timing.pctl_timing.togcnt1u, in pctl_cfg()
630 writel(ddr_timing.noc_timing.noc_timing, &axi_bus->ddrtiming); in phy_cfg()
637 writel(ddr_timing.phy_timing.cl_al, &ddr_phy->ddrphy_reg4a); in phy_cfg()
[all …]
/dports/emulators/qemu42/qemu-4.2.1/roms/u-boot/arch/arm/mach-rockchip/rk3036/
H A Dsdram_rk3036.c43 const struct rk3036_ddr_timing ddr_timing = {0x18c, variable
401 if (freq < ddr_timing.freq) { in phy_dll_bypass_set()
461 (ddr_timing.phy_timing.mr[2] & CMD_ADDR_MASK) << in memory_init()
466 (ddr_timing.phy_timing.mr[3] & CMD_ADDR_MASK) << in memory_init()
471 (ddr_timing.phy_timing.mr[1] & CMD_ADDR_MASK) << in memory_init()
476 (ddr_timing.phy_timing.mr[0] & CMD_ADDR_MASK) << in memory_init()
603 if ((ddr_timing.noc_timing.burstlen << 1) == 4) in pctl_cfg()
608 copy_to_reg(&pctl->togcnt1u, &ddr_timing.pctl_timing.togcnt1u, in pctl_cfg()
629 writel(ddr_timing.noc_timing.noc_timing, &axi_bus->ddrtiming); in phy_cfg()
636 writel(ddr_timing.phy_timing.cl_al, &ddr_phy->ddrphy_reg4a); in phy_cfg()
[all …]
/dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/arch/arm/mach-rockchip/rk3036/
H A Dsdram_rk3036.c44 const struct rk3036_ddr_timing ddr_timing = {0x18c, variable
402 if (freq < ddr_timing.freq) { in phy_dll_bypass_set()
462 (ddr_timing.phy_timing.mr[2] & CMD_ADDR_MASK) << in memory_init()
467 (ddr_timing.phy_timing.mr[3] & CMD_ADDR_MASK) << in memory_init()
472 (ddr_timing.phy_timing.mr[1] & CMD_ADDR_MASK) << in memory_init()
477 (ddr_timing.phy_timing.mr[0] & CMD_ADDR_MASK) << in memory_init()
604 if ((ddr_timing.noc_timing.burstlen << 1) == 4) in pctl_cfg()
609 copy_to_reg(&pctl->togcnt1u, &ddr_timing.pctl_timing.togcnt1u, in pctl_cfg()
630 writel(ddr_timing.noc_timing.noc_timing, &axi_bus->ddrtiming); in phy_cfg()
637 writel(ddr_timing.phy_timing.cl_al, &ddr_phy->ddrphy_reg4a); in phy_cfg()
[all …]
/dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/arch/arm/mach-rockchip/rk3036/
H A Dsdram_rk3036.c44 const struct rk3036_ddr_timing ddr_timing = {0x18c, variable
402 if (freq < ddr_timing.freq) { in phy_dll_bypass_set()
462 (ddr_timing.phy_timing.mr[2] & CMD_ADDR_MASK) << in memory_init()
467 (ddr_timing.phy_timing.mr[3] & CMD_ADDR_MASK) << in memory_init()
472 (ddr_timing.phy_timing.mr[1] & CMD_ADDR_MASK) << in memory_init()
477 (ddr_timing.phy_timing.mr[0] & CMD_ADDR_MASK) << in memory_init()
604 if ((ddr_timing.noc_timing.burstlen << 1) == 4) in pctl_cfg()
609 copy_to_reg(&pctl->togcnt1u, &ddr_timing.pctl_timing.togcnt1u, in pctl_cfg()
630 writel(ddr_timing.noc_timing.noc_timing, &axi_bus->ddrtiming); in phy_cfg()
637 writel(ddr_timing.phy_timing.cl_al, &ddr_phy->ddrphy_reg4a); in phy_cfg()
[all …]
/dports/sysutils/u-boot-nanopi-neo/u-boot-2021.07/arch/arm/mach-rockchip/rk3036/
H A Dsdram_rk3036.c44 const struct rk3036_ddr_timing ddr_timing = {0x18c, variable
402 if (freq < ddr_timing.freq) { in phy_dll_bypass_set()
462 (ddr_timing.phy_timing.mr[2] & CMD_ADDR_MASK) << in memory_init()
467 (ddr_timing.phy_timing.mr[3] & CMD_ADDR_MASK) << in memory_init()
472 (ddr_timing.phy_timing.mr[1] & CMD_ADDR_MASK) << in memory_init()
477 (ddr_timing.phy_timing.mr[0] & CMD_ADDR_MASK) << in memory_init()
604 if ((ddr_timing.noc_timing.burstlen << 1) == 4) in pctl_cfg()
609 copy_to_reg(&pctl->togcnt1u, &ddr_timing.pctl_timing.togcnt1u, in pctl_cfg()
630 writel(ddr_timing.noc_timing.noc_timing, &axi_bus->ddrtiming); in phy_cfg()
637 writel(ddr_timing.phy_timing.cl_al, &ddr_phy->ddrphy_reg4a); in phy_cfg()
[all …]
/dports/sysutils/u-boot-nanopi-a64/u-boot-2021.07/arch/arm/mach-rockchip/rk3036/
H A Dsdram_rk3036.c44 const struct rk3036_ddr_timing ddr_timing = {0x18c, variable
402 if (freq < ddr_timing.freq) { in phy_dll_bypass_set()
462 (ddr_timing.phy_timing.mr[2] & CMD_ADDR_MASK) << in memory_init()
467 (ddr_timing.phy_timing.mr[3] & CMD_ADDR_MASK) << in memory_init()
472 (ddr_timing.phy_timing.mr[1] & CMD_ADDR_MASK) << in memory_init()
477 (ddr_timing.phy_timing.mr[0] & CMD_ADDR_MASK) << in memory_init()
604 if ((ddr_timing.noc_timing.burstlen << 1) == 4) in pctl_cfg()
609 copy_to_reg(&pctl->togcnt1u, &ddr_timing.pctl_timing.togcnt1u, in pctl_cfg()
630 writel(ddr_timing.noc_timing.noc_timing, &axi_bus->ddrtiming); in phy_cfg()
637 writel(ddr_timing.phy_timing.cl_al, &ddr_phy->ddrphy_reg4a); in phy_cfg()
[all …]
/dports/sysutils/u-boot-nanopi-neo-air/u-boot-2021.07/arch/arm/mach-rockchip/rk3036/
H A Dsdram_rk3036.c44 const struct rk3036_ddr_timing ddr_timing = {0x18c, variable
402 if (freq < ddr_timing.freq) { in phy_dll_bypass_set()
462 (ddr_timing.phy_timing.mr[2] & CMD_ADDR_MASK) << in memory_init()
467 (ddr_timing.phy_timing.mr[3] & CMD_ADDR_MASK) << in memory_init()
472 (ddr_timing.phy_timing.mr[1] & CMD_ADDR_MASK) << in memory_init()
477 (ddr_timing.phy_timing.mr[0] & CMD_ADDR_MASK) << in memory_init()
604 if ((ddr_timing.noc_timing.burstlen << 1) == 4) in pctl_cfg()
609 copy_to_reg(&pctl->togcnt1u, &ddr_timing.pctl_timing.togcnt1u, in pctl_cfg()
630 writel(ddr_timing.noc_timing.noc_timing, &axi_bus->ddrtiming); in phy_cfg()
637 writel(ddr_timing.phy_timing.cl_al, &ddr_phy->ddrphy_reg4a); in phy_cfg()
[all …]
/dports/sysutils/u-boot-wandboard/u-boot-2021.07/arch/arm/mach-rockchip/rk3036/
H A Dsdram_rk3036.c44 const struct rk3036_ddr_timing ddr_timing = {0x18c, variable
402 if (freq < ddr_timing.freq) { in phy_dll_bypass_set()
462 (ddr_timing.phy_timing.mr[2] & CMD_ADDR_MASK) << in memory_init()
467 (ddr_timing.phy_timing.mr[3] & CMD_ADDR_MASK) << in memory_init()
472 (ddr_timing.phy_timing.mr[1] & CMD_ADDR_MASK) << in memory_init()
477 (ddr_timing.phy_timing.mr[0] & CMD_ADDR_MASK) << in memory_init()
604 if ((ddr_timing.noc_timing.burstlen << 1) == 4) in pctl_cfg()
609 copy_to_reg(&pctl->togcnt1u, &ddr_timing.pctl_timing.togcnt1u, in pctl_cfg()
630 writel(ddr_timing.noc_timing.noc_timing, &axi_bus->ddrtiming); in phy_cfg()
637 writel(ddr_timing.phy_timing.cl_al, &ddr_phy->ddrphy_reg4a); in phy_cfg()
[all …]
/dports/emulators/qemu-utils/qemu-4.2.1/roms/u-boot/arch/arm/mach-rockchip/rk3036/
H A Dsdram_rk3036.c43 const struct rk3036_ddr_timing ddr_timing = {0x18c, variable
401 if (freq < ddr_timing.freq) { in phy_dll_bypass_set()
461 (ddr_timing.phy_timing.mr[2] & CMD_ADDR_MASK) << in memory_init()
466 (ddr_timing.phy_timing.mr[3] & CMD_ADDR_MASK) << in memory_init()
471 (ddr_timing.phy_timing.mr[1] & CMD_ADDR_MASK) << in memory_init()
476 (ddr_timing.phy_timing.mr[0] & CMD_ADDR_MASK) << in memory_init()
603 if ((ddr_timing.noc_timing.burstlen << 1) == 4) in pctl_cfg()
608 copy_to_reg(&pctl->togcnt1u, &ddr_timing.pctl_timing.togcnt1u, in pctl_cfg()
629 writel(ddr_timing.noc_timing.noc_timing, &axi_bus->ddrtiming); in phy_cfg()
636 writel(ddr_timing.phy_timing.cl_al, &ddr_phy->ddrphy_reg4a); in phy_cfg()
[all …]
/dports/emulators/qemu-guest-agent/qemu-5.0.1/roms/u-boot/arch/arm/mach-rockchip/rk3036/
H A Dsdram_rk3036.c43 const struct rk3036_ddr_timing ddr_timing = {0x18c, variable
401 if (freq < ddr_timing.freq) { in phy_dll_bypass_set()
461 (ddr_timing.phy_timing.mr[2] & CMD_ADDR_MASK) << in memory_init()
466 (ddr_timing.phy_timing.mr[3] & CMD_ADDR_MASK) << in memory_init()
471 (ddr_timing.phy_timing.mr[1] & CMD_ADDR_MASK) << in memory_init()
476 (ddr_timing.phy_timing.mr[0] & CMD_ADDR_MASK) << in memory_init()
603 if ((ddr_timing.noc_timing.burstlen << 1) == 4) in pctl_cfg()
608 copy_to_reg(&pctl->togcnt1u, &ddr_timing.pctl_timing.togcnt1u, in pctl_cfg()
629 writel(ddr_timing.noc_timing.noc_timing, &axi_bus->ddrtiming); in phy_cfg()
636 writel(ddr_timing.phy_timing.cl_al, &ddr_phy->ddrphy_reg4a); in phy_cfg()
[all …]
/dports/sysutils/u-boot-cubieboard/u-boot-2021.07/arch/arm/mach-rockchip/rk3036/
H A Dsdram_rk3036.c44 const struct rk3036_ddr_timing ddr_timing = {0x18c, variable
402 if (freq < ddr_timing.freq) { in phy_dll_bypass_set()
462 (ddr_timing.phy_timing.mr[2] & CMD_ADDR_MASK) << in memory_init()
467 (ddr_timing.phy_timing.mr[3] & CMD_ADDR_MASK) << in memory_init()
472 (ddr_timing.phy_timing.mr[1] & CMD_ADDR_MASK) << in memory_init()
477 (ddr_timing.phy_timing.mr[0] & CMD_ADDR_MASK) << in memory_init()
604 if ((ddr_timing.noc_timing.burstlen << 1) == 4) in pctl_cfg()
609 copy_to_reg(&pctl->togcnt1u, &ddr_timing.pctl_timing.togcnt1u, in pctl_cfg()
630 writel(ddr_timing.noc_timing.noc_timing, &axi_bus->ddrtiming); in phy_cfg()
637 writel(ddr_timing.phy_timing.cl_al, &ddr_phy->ddrphy_reg4a); in phy_cfg()
[all …]
/dports/sysutils/u-boot-clearfog/u-boot-2021.07/arch/arm/mach-rockchip/rk3036/
H A Dsdram_rk3036.c44 const struct rk3036_ddr_timing ddr_timing = {0x18c, variable
402 if (freq < ddr_timing.freq) { in phy_dll_bypass_set()
462 (ddr_timing.phy_timing.mr[2] & CMD_ADDR_MASK) << in memory_init()
467 (ddr_timing.phy_timing.mr[3] & CMD_ADDR_MASK) << in memory_init()
472 (ddr_timing.phy_timing.mr[1] & CMD_ADDR_MASK) << in memory_init()
477 (ddr_timing.phy_timing.mr[0] & CMD_ADDR_MASK) << in memory_init()
604 if ((ddr_timing.noc_timing.burstlen << 1) == 4) in pctl_cfg()
609 copy_to_reg(&pctl->togcnt1u, &ddr_timing.pctl_timing.togcnt1u, in pctl_cfg()
630 writel(ddr_timing.noc_timing.noc_timing, &axi_bus->ddrtiming); in phy_cfg()
637 writel(ddr_timing.phy_timing.cl_al, &ddr_phy->ddrphy_reg4a); in phy_cfg()
[all …]
/dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/arch/arm/mach-rockchip/rk3036/
H A Dsdram_rk3036.c44 const struct rk3036_ddr_timing ddr_timing = {0x18c, variable
402 if (freq < ddr_timing.freq) { in phy_dll_bypass_set()
462 (ddr_timing.phy_timing.mr[2] & CMD_ADDR_MASK) << in memory_init()
467 (ddr_timing.phy_timing.mr[3] & CMD_ADDR_MASK) << in memory_init()
472 (ddr_timing.phy_timing.mr[1] & CMD_ADDR_MASK) << in memory_init()
477 (ddr_timing.phy_timing.mr[0] & CMD_ADDR_MASK) << in memory_init()
604 if ((ddr_timing.noc_timing.burstlen << 1) == 4) in pctl_cfg()
609 copy_to_reg(&pctl->togcnt1u, &ddr_timing.pctl_timing.togcnt1u, in pctl_cfg()
630 writel(ddr_timing.noc_timing.noc_timing, &axi_bus->ddrtiming); in phy_cfg()
637 writel(ddr_timing.phy_timing.cl_al, &ddr_phy->ddrphy_reg4a); in phy_cfg()
[all …]
/dports/sysutils/u-boot-pandaboard/u-boot-2021.07/arch/arm/mach-rockchip/rk3036/
H A Dsdram_rk3036.c44 const struct rk3036_ddr_timing ddr_timing = {0x18c, variable
402 if (freq < ddr_timing.freq) { in phy_dll_bypass_set()
462 (ddr_timing.phy_timing.mr[2] & CMD_ADDR_MASK) << in memory_init()
467 (ddr_timing.phy_timing.mr[3] & CMD_ADDR_MASK) << in memory_init()
472 (ddr_timing.phy_timing.mr[1] & CMD_ADDR_MASK) << in memory_init()
477 (ddr_timing.phy_timing.mr[0] & CMD_ADDR_MASK) << in memory_init()
604 if ((ddr_timing.noc_timing.burstlen << 1) == 4) in pctl_cfg()
609 copy_to_reg(&pctl->togcnt1u, &ddr_timing.pctl_timing.togcnt1u, in pctl_cfg()
630 writel(ddr_timing.noc_timing.noc_timing, &axi_bus->ddrtiming); in phy_cfg()
637 writel(ddr_timing.phy_timing.cl_al, &ddr_phy->ddrphy_reg4a); in phy_cfg()
[all …]

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