/dports/devel/llvm70/llvm-7.0.1.src/lib/Target/Hexagon/ |
H A D | HexagonPatterns.td | 36 // deliberately chosen (other than to create a logical structure of 39 // 2. Maintain the logical structure of the file, try to put new patterns 1199 def: Pat<(and I32:$Rs, anyimm:$s10), (A2_andir I32:$Rs, imm:$s10)>; 1615 let AddedComplexity = 20 in { // Complexity greater than cmp reg-imm. 1626 let AddedComplexity = 20 in { // Complexity greater than compare reg-imm. 1646 let AddedComplexity = 20 in { // Complexity greater than cmp reg-imm. 1748 // - base reg [+ imm] 1777 // - base reg [+ imm] 1818 // Don't match for u2==0, instead use reg+imm for those cases. 2635 // and reg [all …]
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/dports/devel/llvm90/llvm-9.0.1.src/lib/Target/Hexagon/ |
H A D | HexagonPatterns.td | 35 // deliberately chosen (other than to create a logical structure of 38 // 2. Maintain the logical structure of the file, try to put new patterns 1292 def: Pat<(and I32:$Rs, anyimm:$s10), (A2_andir I32:$Rs, imm:$s10)>; 1709 let AddedComplexity = 20 in { // Complexity greater than cmp reg-imm. 1720 let AddedComplexity = 20 in { // Complexity greater than compare reg-imm. 1740 let AddedComplexity = 20 in { // Complexity greater than cmp reg-imm. 1842 // - base reg [+ imm] 1871 // - base reg [+ imm] 1912 // Don't match for u2==0, instead use reg+imm for those cases. 2794 // and reg [all …]
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/dports/devel/llvm80/llvm-8.0.1.src/lib/Target/Hexagon/ |
H A D | HexagonPatterns.td | 36 // deliberately chosen (other than to create a logical structure of 39 // 2. Maintain the logical structure of the file, try to put new patterns 1293 def: Pat<(and I32:$Rs, anyimm:$s10), (A2_andir I32:$Rs, imm:$s10)>; 1710 let AddedComplexity = 20 in { // Complexity greater than cmp reg-imm. 1721 let AddedComplexity = 20 in { // Complexity greater than compare reg-imm. 1741 let AddedComplexity = 20 in { // Complexity greater than cmp reg-imm. 1843 // - base reg [+ imm] 1872 // - base reg [+ imm] 1913 // Don't match for u2==0, instead use reg+imm for those cases. 2795 // and reg [all …]
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/dports/security/clamav-lts/clamav-0.103.5/libclamav/c++/llvm/lib/Target/PowerPC/ |
H A D | PPCInstrInfo.td | 313 let MIOperandInfo = (ops i32imm:$imm, ptr_rc:$reg); 321 let MIOperandInfo = (ops i32imm:$imm, ptr_rc:$reg); 405 "b${p:cc}lr ${p:reg}", BrB, 426 "b${cond:cc} ${cond:reg}, $dst" 1057 // XL-Form instructions. condition register logical ops. 1287 // and 4/8 byte forms for the result and operand type.. 1363 def : Pat<(i32 imm:$imm), 1371 def : Pat<(add GPRC:$in, imm:$imm), 1374 def : Pat<(or GPRC:$in, imm:$imm), 1377 def : Pat<(xor GPRC:$in, imm:$imm), [all …]
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/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/lib/Target/Hexagon/ |
H A D | HexagonPatterns.td | 35 // deliberately chosen (other than to create a logical structure of 38 // 2. Maintain the logical structure of the file, try to put new patterns 1824 let AddedComplexity = 20 in { // Complexity greater than cmp reg-imm. 1849 let AddedComplexity = 20 in { // Complexity greater than compare reg-imm. 1872 let AddedComplexity = 20 in { // Complexity greater than cmp reg-imm. 1987 // - base reg [+ imm] 2016 // - base reg [+ imm] 2039 // Pattern to select load reg reg-indexed: Rs + Rt<<0. 2057 // Don't match for u2==0, instead use reg+imm for those cases. 2966 // and reg [all …]
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/dports/graphics/llvm-mesa/llvm-13.0.1.src/lib/Target/Hexagon/ |
H A D | HexagonPatterns.td | 35 // deliberately chosen (other than to create a logical structure of 38 // 2. Maintain the logical structure of the file, try to put new patterns 1824 let AddedComplexity = 20 in { // Complexity greater than cmp reg-imm. 1849 let AddedComplexity = 20 in { // Complexity greater than compare reg-imm. 1872 let AddedComplexity = 20 in { // Complexity greater than cmp reg-imm. 1987 // - base reg [+ imm] 2016 // - base reg [+ imm] 2039 // Pattern to select load reg reg-indexed: Rs + Rt<<0. 2057 // Don't match for u2==0, instead use reg+imm for those cases. 2966 // and reg [all …]
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/dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonPatterns.td | 35 // deliberately chosen (other than to create a logical structure of 38 // 2. Maintain the logical structure of the file, try to put new patterns 1824 let AddedComplexity = 20 in { // Complexity greater than cmp reg-imm. 1849 let AddedComplexity = 20 in { // Complexity greater than compare reg-imm. 1872 let AddedComplexity = 20 in { // Complexity greater than cmp reg-imm. 1987 // - base reg [+ imm] 2016 // - base reg [+ imm] 2039 // Pattern to select load reg reg-indexed: Rs + Rt<<0. 2057 // Don't match for u2==0, instead use reg+imm for those cases. 2966 // and reg [all …]
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/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/lib/Target/Hexagon/ |
H A D | HexagonPatterns.td | 35 // deliberately chosen (other than to create a logical structure of 38 // 2. Maintain the logical structure of the file, try to put new patterns 1824 let AddedComplexity = 20 in { // Complexity greater than cmp reg-imm. 1849 let AddedComplexity = 20 in { // Complexity greater than compare reg-imm. 1872 let AddedComplexity = 20 in { // Complexity greater than cmp reg-imm. 1987 // - base reg [+ imm] 2016 // - base reg [+ imm] 2039 // Pattern to select load reg reg-indexed: Rs + Rt<<0. 2057 // Don't match for u2==0, instead use reg+imm for those cases. 2966 // and reg [all …]
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/dports/devel/wasi-compiler-rt13/llvm-project-13.0.1.src/llvm/lib/Target/Hexagon/ |
H A D | HexagonPatterns.td | 35 // deliberately chosen (other than to create a logical structure of 38 // 2. Maintain the logical structure of the file, try to put new patterns 1824 let AddedComplexity = 20 in { // Complexity greater than cmp reg-imm. 1849 let AddedComplexity = 20 in { // Complexity greater than compare reg-imm. 1872 let AddedComplexity = 20 in { // Complexity greater than cmp reg-imm. 1987 // - base reg [+ imm] 2016 // - base reg [+ imm] 2039 // Pattern to select load reg reg-indexed: Rs + Rt<<0. 2057 // Don't match for u2==0, instead use reg+imm for those cases. 2966 // and reg [all …]
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/dports/devel/llvm13/llvm-project-13.0.1.src/llvm/lib/Target/Hexagon/ |
H A D | HexagonPatterns.td | 35 // deliberately chosen (other than to create a logical structure of 38 // 2. Maintain the logical structure of the file, try to put new patterns 1824 let AddedComplexity = 20 in { // Complexity greater than cmp reg-imm. 1849 let AddedComplexity = 20 in { // Complexity greater than compare reg-imm. 1872 let AddedComplexity = 20 in { // Complexity greater than cmp reg-imm. 1987 // - base reg [+ imm] 2016 // - base reg [+ imm] 2039 // Pattern to select load reg reg-indexed: Rs + Rt<<0. 2057 // Don't match for u2==0, instead use reg+imm for those cases. 2966 // and reg [all …]
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/dports/devel/llvm12/llvm-project-12.0.1.src/llvm/lib/Target/Hexagon/ |
H A D | HexagonPatterns.td | 35 // deliberately chosen (other than to create a logical structure of 38 // 2. Maintain the logical structure of the file, try to put new patterns 1809 let AddedComplexity = 20 in { // Complexity greater than cmp reg-imm. 1834 let AddedComplexity = 20 in { // Complexity greater than compare reg-imm. 1857 let AddedComplexity = 20 in { // Complexity greater than cmp reg-imm. 1969 // - base reg [+ imm] 1998 // - base reg [+ imm] 2021 // Pattern to select load reg reg-indexed: Rs + Rt<<0. 2039 // Don't match for u2==0, instead use reg+imm for those cases. 2921 // and reg [all …]
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/dports/devel/wasi-compiler-rt12/llvm-project-12.0.1.src/llvm/lib/Target/Hexagon/ |
H A D | HexagonPatterns.td | 35 // deliberately chosen (other than to create a logical structure of 38 // 2. Maintain the logical structure of the file, try to put new patterns 1809 let AddedComplexity = 20 in { // Complexity greater than cmp reg-imm. 1834 let AddedComplexity = 20 in { // Complexity greater than compare reg-imm. 1857 let AddedComplexity = 20 in { // Complexity greater than cmp reg-imm. 1969 // - base reg [+ imm] 1998 // - base reg [+ imm] 2021 // Pattern to select load reg reg-indexed: Rs + Rt<<0. 2039 // Don't match for u2==0, instead use reg+imm for those cases. 2921 // and reg [all …]
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/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/llvm/llvm/lib/Target/Hexagon/ |
H A D | HexagonPatterns.td | 35 // deliberately chosen (other than to create a logical structure of 38 // 2. Maintain the logical structure of the file, try to put new patterns 1818 let AddedComplexity = 20 in { // Complexity greater than cmp reg-imm. 1843 let AddedComplexity = 20 in { // Complexity greater than compare reg-imm. 1866 let AddedComplexity = 20 in { // Complexity greater than cmp reg-imm. 1978 // - base reg [+ imm] 2007 // - base reg [+ imm] 2030 // Pattern to select load reg reg-indexed: Rs + Rt<<0. 2048 // Don't match for u2==0, instead use reg+imm for those cases. 2930 // and reg [all …]
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/dports/devel/llvm-cheri/llvm-project-37c49ff00e3eadce5d8703fdc4497f28458c64a8/llvm/lib/Target/Hexagon/ |
H A D | HexagonPatterns.td | 35 // deliberately chosen (other than to create a logical structure of 38 // 2. Maintain the logical structure of the file, try to put new patterns 1798 let AddedComplexity = 20 in { // Complexity greater than cmp reg-imm. 1823 let AddedComplexity = 20 in { // Complexity greater than compare reg-imm. 1846 let AddedComplexity = 20 in { // Complexity greater than cmp reg-imm. 1958 // - base reg [+ imm] 1987 // - base reg [+ imm] 2010 // Pattern to select load reg reg-indexed: Rs + Rt<<0. 2028 // Don't match for u2==0, instead use reg+imm for those cases. 2910 // and reg [all …]
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/dports/devel/llvm11/llvm-11.0.1.src/lib/Target/Hexagon/ |
H A D | HexagonPatterns.td | 35 // deliberately chosen (other than to create a logical structure of 38 // 2. Maintain the logical structure of the file, try to put new patterns 1798 let AddedComplexity = 20 in { // Complexity greater than cmp reg-imm. 1823 let AddedComplexity = 20 in { // Complexity greater than compare reg-imm. 1846 let AddedComplexity = 20 in { // Complexity greater than cmp reg-imm. 1958 // - base reg [+ imm] 1987 // - base reg [+ imm] 2010 // Pattern to select load reg reg-indexed: Rs + Rt<<0. 2028 // Don't match for u2==0, instead use reg+imm for those cases. 2910 // and reg [all …]
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/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonPatterns.td | 35 // deliberately chosen (other than to create a logical structure of 38 // 2. Maintain the logical structure of the file, try to put new patterns 1756 let AddedComplexity = 20 in { // Complexity greater than cmp reg-imm. 1781 let AddedComplexity = 20 in { // Complexity greater than compare reg-imm. 1804 let AddedComplexity = 20 in { // Complexity greater than cmp reg-imm. 1916 // - base reg [+ imm] 1945 // - base reg [+ imm] 1968 // Pattern to select load reg reg-indexed: Rs + Rt<<0. 1986 // Don't match for u2==0, instead use reg+imm for those cases. 2868 // and reg [all …]
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/dports/devel/llvm10/llvm-10.0.1.src/lib/Target/Hexagon/ |
H A D | HexagonPatterns.td | 35 // deliberately chosen (other than to create a logical structure of 38 // 2. Maintain the logical structure of the file, try to put new patterns 1756 let AddedComplexity = 20 in { // Complexity greater than cmp reg-imm. 1781 let AddedComplexity = 20 in { // Complexity greater than compare reg-imm. 1804 let AddedComplexity = 20 in { // Complexity greater than cmp reg-imm. 1916 // - base reg [+ imm] 1945 // - base reg [+ imm] 1968 // Pattern to select load reg reg-indexed: Rs + Rt<<0. 1986 // Don't match for u2==0, instead use reg+imm for those cases. 2868 // and reg [all …]
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/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
H A D | HexagonPatterns.td | 35 // deliberately chosen (other than to create a logical structure of 38 // 2. Maintain the logical structure of the file, try to put new patterns 1756 let AddedComplexity = 20 in { // Complexity greater than cmp reg-imm. 1781 let AddedComplexity = 20 in { // Complexity greater than compare reg-imm. 1804 let AddedComplexity = 20 in { // Complexity greater than cmp reg-imm. 1916 // - base reg [+ imm] 1945 // - base reg [+ imm] 1968 // Pattern to select load reg reg-indexed: Rs + Rt<<0. 1986 // Don't match for u2==0, instead use reg+imm for those cases. 2868 // and reg [all …]
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/dports/devel/llvm10/llvm-10.0.1.src/lib/Target/PowerPC/ |
H A D | PPCInstrInfo.td | 839 let MIOperandInfo = (ops dispRI:$imm, ptr_rc_nor0:$reg); 849 let MIOperandInfo = (ops dispRIX:$imm, ptr_rc_nor0:$reg); 855 let MIOperandInfo = (ops dispRIX16:$imm, ptr_rc_nor0:$reg); 861 let MIOperandInfo = (ops dispSPE8:$imm, ptr_rc_nor0:$reg); 867 let MIOperandInfo = (ops dispSPE4:$imm, ptr_rc_nor0:$reg); 873 let MIOperandInfo = (ops dispSPE2:$imm, ptr_rc_nor0:$reg); 2583 // XL-Form instructions. condition register logical ops. 2591 // condition-register logical instructions have preferred forms. Specifically, 2983 // and 4/8 byte forms for the result and operand type.. 3076 def : Pat<(i32 imm:$imm), [all …]
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/dports/www/chromium-legacy/chromium-88.0.4324.182/third_party/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
H A D | PPCInstrInfo.td | 839 let MIOperandInfo = (ops dispRI:$imm, ptr_rc_nor0:$reg); 849 let MIOperandInfo = (ops dispRIX:$imm, ptr_rc_nor0:$reg); 855 let MIOperandInfo = (ops dispRIX16:$imm, ptr_rc_nor0:$reg); 861 let MIOperandInfo = (ops dispSPE8:$imm, ptr_rc_nor0:$reg); 867 let MIOperandInfo = (ops dispSPE4:$imm, ptr_rc_nor0:$reg); 873 let MIOperandInfo = (ops dispSPE2:$imm, ptr_rc_nor0:$reg); 2583 // XL-Form instructions. condition register logical ops. 2591 // condition-register logical instructions have preferred forms. Specifically, 2983 // and 4/8 byte forms for the result and operand type.. 3076 def : Pat<(i32 imm:$imm), [all …]
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/dports/devel/tinygo/tinygo-0.14.1/llvm-project/llvm/lib/Target/PowerPC/ |
H A D | PPCInstrInfo.td | 839 let MIOperandInfo = (ops dispRI:$imm, ptr_rc_nor0:$reg); 849 let MIOperandInfo = (ops dispRIX:$imm, ptr_rc_nor0:$reg); 855 let MIOperandInfo = (ops dispRIX16:$imm, ptr_rc_nor0:$reg); 861 let MIOperandInfo = (ops dispSPE8:$imm, ptr_rc_nor0:$reg); 867 let MIOperandInfo = (ops dispSPE4:$imm, ptr_rc_nor0:$reg); 873 let MIOperandInfo = (ops dispSPE2:$imm, ptr_rc_nor0:$reg); 2583 // XL-Form instructions. condition register logical ops. 2591 // condition-register logical instructions have preferred forms. Specifically, 2983 // and 4/8 byte forms for the result and operand type.. 3076 def : Pat<(i32 imm:$imm), [all …]
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/dports/devel/llvm-devel/llvm-project-f05c95f10fc1d8171071735af8ad3a9e87633120/llvm/lib/Target/PowerPC/ |
H A D | PPCInstrInfo.td | 971 let MIOperandInfo = (ops dispRI34:$imm, ptr_rc_nor0:$reg); 979 let MIOperandInfo = (ops dispRI34:$imm, immZero:$reg); 1044 let MIOperandInfo = (ops dispRI:$imm, ptr_rc_nor0:$reg); 1056 let MIOperandInfo = (ops dispRIX:$imm, ptr_rc_nor0:$reg); 1071 let MIOperandInfo = (ops dispRIX16:$imm, ptr_rc_nor0:$reg); 1078 let MIOperandInfo = (ops dispSPE8:$imm, ptr_rc_nor0:$reg); 1085 let MIOperandInfo = (ops dispSPE4:$imm, ptr_rc_nor0:$reg); 1092 let MIOperandInfo = (ops dispSPE2:$imm, ptr_rc_nor0:$reg); 2892 // XL-Form instructions. condition register logical ops. 2900 // condition-register logical instructions have preferred forms. Specifically, [all …]
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/dports/devel/wasi-libcxx/llvm-project-13.0.1.src/llvm/lib/Target/PowerPC/ |
H A D | PPCInstrInfo.td | 971 let MIOperandInfo = (ops dispRI34:$imm, ptr_rc_nor0:$reg); 979 let MIOperandInfo = (ops dispRI34:$imm, immZero:$reg); 1044 let MIOperandInfo = (ops dispRI:$imm, ptr_rc_nor0:$reg); 1056 let MIOperandInfo = (ops dispRIX:$imm, ptr_rc_nor0:$reg); 1071 let MIOperandInfo = (ops dispRIX16:$imm, ptr_rc_nor0:$reg); 1078 let MIOperandInfo = (ops dispSPE8:$imm, ptr_rc_nor0:$reg); 1085 let MIOperandInfo = (ops dispSPE4:$imm, ptr_rc_nor0:$reg); 1092 let MIOperandInfo = (ops dispSPE2:$imm, ptr_rc_nor0:$reg); 2890 // XL-Form instructions. condition register logical ops. 2898 // condition-register logical instructions have preferred forms. Specifically, [all …]
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/dports/graphics/llvm-mesa/llvm-13.0.1.src/lib/Target/PowerPC/ |
H A D | PPCInstrInfo.td | 971 let MIOperandInfo = (ops dispRI34:$imm, ptr_rc_nor0:$reg); 979 let MIOperandInfo = (ops dispRI34:$imm, immZero:$reg); 1044 let MIOperandInfo = (ops dispRI:$imm, ptr_rc_nor0:$reg); 1056 let MIOperandInfo = (ops dispRIX:$imm, ptr_rc_nor0:$reg); 1071 let MIOperandInfo = (ops dispRIX16:$imm, ptr_rc_nor0:$reg); 1078 let MIOperandInfo = (ops dispSPE8:$imm, ptr_rc_nor0:$reg); 1085 let MIOperandInfo = (ops dispSPE4:$imm, ptr_rc_nor0:$reg); 1092 let MIOperandInfo = (ops dispSPE2:$imm, ptr_rc_nor0:$reg); 2890 // XL-Form instructions. condition register logical ops. 2898 // condition-register logical instructions have preferred forms. Specifically, [all …]
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/dports/lang/rust/rustc-1.58.1-src/src/llvm-project/llvm/lib/Target/PowerPC/ |
H A D | PPCInstrInfo.td | 971 let MIOperandInfo = (ops dispRI34:$imm, ptr_rc_nor0:$reg); 979 let MIOperandInfo = (ops dispRI34:$imm, immZero:$reg); 1044 let MIOperandInfo = (ops dispRI:$imm, ptr_rc_nor0:$reg); 1056 let MIOperandInfo = (ops dispRIX:$imm, ptr_rc_nor0:$reg); 1071 let MIOperandInfo = (ops dispRIX16:$imm, ptr_rc_nor0:$reg); 1078 let MIOperandInfo = (ops dispSPE8:$imm, ptr_rc_nor0:$reg); 1085 let MIOperandInfo = (ops dispSPE4:$imm, ptr_rc_nor0:$reg); 1092 let MIOperandInfo = (ops dispSPE2:$imm, ptr_rc_nor0:$reg); 2890 // XL-Form instructions. condition register logical ops. 2898 // condition-register logical instructions have preferred forms. Specifically, [all …]
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