/dports/cad/gplcver/gplcver-2.12a.src/tests_and_examples/install.tst/ |
H A D | dffn.plg | 4 30 -- top.pipe1.p[1].dff[2]: positive clock edge old q=x d=x 5 30 -- top.pipe1.p[1].dff[1]: positive clock edge old q=x d=x 6 30 -- top.pipe1.p[1].dff[0]: positive clock edge old q=x d=x 7 30 -- top.pipe1.p[2].dff[2]: positive clock edge old q=x d=x 8 30 -- top.pipe1.p[2].dff[1]: positive clock edge old q=x d=x 9 30 -- top.pipe1.p[2].dff[0]: positive clock edge old q=x d=x 10 30 -- top.pipe1.p[3].dff[2]: positive clock edge old q=x d=x 11 30 -- top.pipe1.p[3].dff[1]: positive clock edge old q=x d=x 12 30 -- top.pipe1.p[3].dff[0]: positive clock edge old q=x d=x 13 30 -- top.pipe1.p[4].dff[2]: positive clock edge old q=x d=0 [all …]
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/dports/math/freefem++/FreeFem-sources-4.6/plugin/seq/ |
H A D | mmg3d-v4.0.cpp | 72 dff->mesh = pTh; in set_mesh() 115 ffassert(dff->mesh); in set_v() 131 ffassert(dff->mesh); in set_elmt() 309 DataFF dff; in operator ( )() local 312 dff.typesol = 0; in operator ( )() 313 dff.np = pTh->nv; in operator ( )() 314 dff.mesh = pTh; in operator ( )() 317 dff.sol = 0; in operator ( )() 318 dff.mov = 0; in operator ( )() 321 dff.set_v = set_v; in operator ( )() [all …]
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/dports/cad/yosys/yosys-yosys-0.12/passes/pmgen/ |
H A D | ice40_dsp.pmg | 17 udata <Cell*> dff 67 if (dff) { 68 ffA = dff; 80 if (dff) { 81 ffB = dff; 96 if (dff) { 140 if (dff) { 241 if (dff) { 257 } else if (dff && dff->hasPort(\SRST)) { 357 dff = ff; [all …]
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H A D | xilinx_dsp48a.pmg | 98 if (dff) { 99 ffB1 = dff; 139 if (dff) { 170 if (dff) { 212 if (dff) { 213 ffD = dff; 225 if (dff) { 226 ffM = dff; 271 if (dff) { 362 dff = ff; [all …]
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H A D | xilinx_dsp.pmg | 117 if (dff) { 118 ffAD = dff; 165 if (dff) { 183 if (dff) { 214 if (dff) { 256 if (dff) { 257 ffD = dff; 269 if (dff) { 270 ffM = dff; 423 dff = ff; [all …]
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/dports/cad/ghdl/ghdl-1.0.0/testsuite/gna/bug075/ |
H A D | dff.vhdl | 5 entity dff is entity 10 end entity dff; 12 architecture behave of dff is 25 entity dff is entity 26 end entity dff; 28 architecture behave of dff is 29 component dff is 40 dff port map ( d_in, clk_in, q_out);
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/dports/net/tcpdump/tcpdump-4.99.1/tests/ |
H A D | vrrp.out | 6 …6 21:55:19.064377 IP6 fe80::d6ca:6dff:fe66:cf60 > ff02::12: VRRPv3, Advertisement, vrid 45, prio … 7 …7 21:55:19.064509 IP6 fe80::d6ca:6dff:fe66:cf60 > ff02::12: VRRPv3, Advertisement, vrid 46, prio … 11 …11 21:55:29.068063 IP6 fe80::d6ca:6dff:fe66:cf60 > ff02::12: VRRPv3, Advertisement, vrid 46, prio… 12 …12 21:55:29.068132 IP6 fe80::d6ca:6dff:fe66:cf60 > ff02::12: VRRPv3, Advertisement, vrid 45, prio… 17 …17 21:55:39.070934 IP6 fe80::d6ca:6dff:fe66:cf60 > ff02::12: VRRPv3, Advertisement, vrid 45, prio… 18 …18 21:55:39.071010 IP6 fe80::d6ca:6dff:fe66:cf60 > ff02::12: VRRPv3, Advertisement, vrid 46, prio… 22 …22 21:55:47.047012 IP6 fe80::d6ca:6dff:fe72:b1da > ff02::12: VRRPv3, Advertisement, vrid 46, prio… 23 …23 21:55:47.047042 IP6 fe80::d6ca:6dff:fe72:b1da > ff02::12: VRRPv3, Advertisement, vrid 45, prio… 27 …27 21:55:57.042754 IP6 fe80::d6ca:6dff:fe72:b1da > ff02::12: VRRPv3, Advertisement, vrid 45, prio… 28 …28 21:55:57.042778 IP6 fe80::d6ca:6dff:fe72:b1da > ff02::12: VRRPv3, Advertisement, vrid 46, prio… [all …]
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H A D | vrrp-v.out | 11 …6 21:55:19.064377 IP6 (hlim 255, next-header VRRP (112) payload length: 40) fe80::d6ca:6dff:fe66:… 20 …12 21:55:29.068132 IP6 (hlim 255, next-header VRRP (112) payload length: 40) fe80::d6ca:6dff:fe66… 29 …17 21:55:39.070934 IP6 (hlim 255, next-header VRRP (112) payload length: 40) fe80::d6ca:6dff:fe66… 38 …23 21:55:47.047042 IP6 (hlim 255, next-header VRRP (112) payload length: 40) fe80::d6ca:6dff:fe72… 45 …27 21:55:57.042754 IP6 (hlim 255, next-header VRRP (112) payload length: 40) fe80::d6ca:6dff:fe72… 54 …33 21:56:07.047062 IP6 (hlim 255, next-header VRRP (112) payload length: 40) fe80::d6ca:6dff:fe72… 60 …37 21:56:16.860206 IP6 (hlim 255, next-header VRRP (112) payload length: 40) fe80::d6ca:6dff:fe66… 68 …42 21:56:26.860037 IP6 (hlim 255, next-header VRRP (112) payload length: 40) fe80::d6ca:6dff:fe66… 76 …47 21:56:36.859786 IP6 (hlim 255, next-header VRRP (112) payload length: 40) fe80::d6ca:6dff:fe66… 86 …53 21:56:46.860627 IP6 (hlim 255, next-header VRRP (112) payload length: 40) fe80::d6ca:6dff:fe66… [all …]
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/dports/cad/yosys/yosys-yosys-0.12/tests/opt/ |
H A D | opt_merge_init.ys | 3 \$dff #( 11 \$dff #( 23 select -assert-count 1 t:$dff 30 \$dff #( 38 \$dff #( 50 select -assert-count 1 t:$dff 57 \$dff #( 65 \$dff #( 77 select -assert-count 2 t:$dff
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/dports/devel/RStudio/rstudio-2021.09.1-372/src/gwt/src/org/rstudio/studio/client/workbench/views/vcs/common/diff/ |
H A D | UnifiedEmitter.java | 226 private Line dff; // Points to the current diff line field in UnifiedEmitter.OutputLinesGenerator 251 while (ctx != null && dff != null) in OutputLinesGenerator() 299 while (dff != null) in OutputLinesGenerator() 321 skew = writeDiffLine(output, dff, skew); in dffPop() 322 dff = dffit.hasNext() ? dffit.next() : null; in dffPop() 353 switch (dff.getType()) in writeDiffLine() 357 dff.getOldLine() + skew, in writeDiffLine() 358 dff.getText(), in writeDiffLine() 359 dff.getDiffIndex())); in writeDiffLine() 365 dff.getText(), in writeDiffLine() [all …]
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/dports/net-im/gloox/gloox-1.0.24/src/ |
H A D | siprofileft.cpp | 92 dff->setOptions( sm ); in requestFT() 109 DataFormField* dff = new DataFormField( "stream-method" ); in acceptFT() local 114 dff->setValue( XMLNS_BYTESTREAMS ); in acceptFT() 117 dff->setValue( XMLNS_IBB ); in acceptFT() 126 dff->setValue( XMLNS_IQ_OOB ); in acceptFT() 130 df.addField( dff ); in acceptFT() 201 if( dff ) in handleSIRequest() 203 const StringMultiMap& options = dff->options(); in handleSIRequest() 236 if( dff ) in handleSIRequestResult() 245 if( dff->value() == XMLNS_IBB ) in handleSIRequestResult() [all …]
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/dports/cad/ghdl/ghdl-1.0.0/testsuite/gna/bug063/ |
H A D | testsuite.sh | 5 analyze_failure dff.vhdl 2> dff.out 6 diff --strip-trailing-cr dff.out dff.expected 8 rm -f dff.out
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H A D | dff.expected | 1 dff.vhdl:10:25: invalid use of UTF8 character for ' 2 dff.vhdl:11:23: invalid use of UTF8 character for ' 3 dff.vhdl:12:23: invalid use of UTF8 character for ' 4 dff.vhdl:12:42: invalid use of UTF8 character for '
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/dports/cad/yosys/yosys-yosys-0.12/manual/APPNOTE_011_Design_Investigation/ |
H A D | submod.ys | 5 select -set outstage y %ci2:+$dff[Q,D] %ci*:-$mux[S]:-$dff 6 select -set selstage y %ci2:+$dff[Q,D] %ci*:-$dff @outstage %d 7 select -set scramble mem* %ci2 %ci*:-$dff mem* %d @selstage %d
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/dports/cad/ghdl/ghdl-1.0.0/testsuite/gna/bug090/ |
H A D | hang7.vhdl | 4 entity dff is entity 10 end dff; 12 architecture behav of dff is 34 component dff is 42 mydff : entity work.dff 46 dff2 : dff
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H A D | crash9.vhdl | 4 entity dff is entity 10 end dff; 12 architecture behav of dff is 34 component dff is 42 mydff : entity work.dff 46 dff2 : dff
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H A D | crash6.vhdl | 4 entity dff is entity 10 end dff; 12 architecture behav of dff is 34 component dff is 42 mydff : entity work.dff 46 dff2 : dff
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H A D | crash7.vhdl | 4 entity dff is entity 10 end dff; 12 architecture behav of dff is 34 component dff is 42 mydff : entity work.dff 46 dff2 : dff
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/dports/science/afni/afni-AFNI_21.3.16/src/ |
H A D | FIRdesign.c | 29 double fbot=-666.9 , ftop=-999.9 , df,dff , fdel , TR=1.0 , dqq ; in main() local 154 fbot *= TR ; ftop *= TR ; df = 1.0/ntap ; fdel = 1.1*df ; dff = 1.0444*df ; in main() 191 band[2*nband] = 0.0 ; band[2*nband+1] = fbot-dff ; in main() 199 band[2*nband] = fbot+dff ; band[2*nband+1] = (ftop < 0.5) ? ftop-dff : 0.5 ; in main() 201 band[2*nband] = 0.0 ; band[2*nband+1] = ftop-dff ; in main() 209 band[2*nband] = ftop+dff ; band[2*nband+1] = 0.5 ; in main()
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/dports/math/reduce/Reduce-svn5758-src/packages/specfn/ |
H A D | constre.red | 57 dff(dffpointer + 10) := sub(x=x^q,dff(dffpointer)); 60 write "=> f := ",dff(dffpointer + 10)>>; 67 dff(dffpointer + 10) := df2 := x^nn * dff(dffpointer); 86 dff(dffpointer + 10) := df2 := x^(-m1)*dff(dffpointer); 102 dff(dffpointer + i) := df(dff(dffpointer + i-1),x); 103 c0 := limit(dff(dffpointer + i),x,0); 106 ,dff(dffpointer + i),",",x,",",0;
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H A D | simplede.red | 38 array dff(50) >>; 74 dff(0) := f; 79 << dff(degreeofde) := df(dff(degreeofde-1),x); 80 eqq := dff(degreeofde) + 169 dff(0) := f; 183 << dff(degreeofde) := df(dff(degreeofde-1),x); 405 dff(dffpointer + 10) := sub(x=x^q,dff(dffpointer)); 415 dff(dffpointer + 10) := df2 := x^nn * dff(dffpointer); 430 dff(dffpointer + 10) := df2 := x^(-m1)*dff(dffpointer); 454 dff(dffpointer + 10):=dff(dffpointer) -lterm; [all …]
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/dports/cad/yosys/yosys-yosys-0.12/tests/techmap/ |
H A D | dfflegalize_dff_init.ys | 55 dff dff_(.C(C), .D(D), .Q(Q[1:0])); 107 select -assert-count 1 dff/t:$_NOT_ 115 select -assert-count 0 dff/t:$_MUX_ 129 select -assert-count 5 dff/t:$_NOT_ 137 select -assert-count 0 dff/t:$_MUX_ 154 select -assert-count 1 dff/t:$_NOT_ 162 select -assert-count 0 dff/t:$_MUX_ 176 select -assert-count 5 dff/t:$_NOT_ 184 select -assert-count 0 dff/t:$_MUX_ 201 select -assert-count 1 dff/t:$_NOT_ [all …]
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/dports/graphics/qt5-3d/kde-qt3d-5.15.2p39/src/extras/text/ |
H A D | qdistancefieldglyphcache.cpp | 290 DistanceFieldFont *dff = new DistanceFieldFont(actualFont, useDoubleRes, nullptr); in getOrCreateDistanceFieldFont() local 291 m_fonts.insert(key, dff); in getOrCreateDistanceFieldFont() 292 return dff; in getOrCreateDistanceFieldFont() 320 QDistanceFieldGlyphCache::Glyph refAndGetGlyph(DistanceFieldFont *dff, quint32 glyph) in refAndGetGlyph() argument 324 if (dff) { in refAndGetGlyph() 325 const auto entry = dff->refGlyph(glyph); in refAndGetGlyph() 340 DistanceFieldFont *dff = getOrCreateDistanceFieldFont(run.rawFont()); in refGlyphs() local 345 ret << refAndGetGlyph(dff, glyph); in refGlyphs() 357 DistanceFieldFont *dff = getOrCreateDistanceFieldFont(run.rawFont()); in derefGlyphs() local 361 dff->derefGlyph(glyph); in derefGlyphs()
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/dports/cad/yosys/yosys-yosys-0.12/tests/arch/xilinx/ |
H A D | dffs.ys | 4 hierarchy -top dff 8 cd dff # Constrain all select calls below inside the top module 26 hierarchy -top dff 28 equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -abc9 -dff -noiopad # equivalency check 30 cd dff # Constrain all select calls below inside the top module 39 equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -abc9 -dff -noiopad # equivalency check
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/dports/cad/yosys/yosys-yosys-0.12/tests/asicworld/ |
H A D | code_verilog_tutorial_if_else.v | 3 reg dff; register 8 dff <= 0; 10 dff <= din;
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