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/dports/multimedia/v4l-utils/linux-5.13-rc2/drivers/clk/imx/
H A Dclk-sscg-pll.c72 int divr1, divf1; member
214 do_div(vco1, temp_setup->divr1 + 1); in clk_sscg_divf1_lookup()
233 for (temp_setup->divr1 = 0; temp_setup->divr1 <= PLL_DIVR1_MAX; in clk_sscg_divr1_lookup()
234 temp_setup->divr1++) { in clk_sscg_divr1_lookup()
236 do_div(temp_setup->ref_div1, temp_setup->divr1 + 1); in clk_sscg_divr1_lookup()
331 u32 val, divr1, divf1, divr2, divf2, divq; in clk_sscg_pll_recalc_rate() local
335 divr1 = FIELD_GET(PLL_DIVR1_MASK, val); in clk_sscg_pll_recalc_rate()
352 do_div(temp64, (divr1 + 1) * (divr2 + 1) * (divq + 1)); in clk_sscg_pll_recalc_rate()
376 val |= FIELD_PREP(PLL_DIVR1_MASK, setup->divr1); in clk_sscg_pll_set_rate()
/dports/multimedia/v4l_compat/linux-5.13-rc2/drivers/clk/imx/
H A Dclk-sscg-pll.c72 int divr1, divf1; member
214 do_div(vco1, temp_setup->divr1 + 1); in clk_sscg_divf1_lookup()
233 for (temp_setup->divr1 = 0; temp_setup->divr1 <= PLL_DIVR1_MAX; in clk_sscg_divr1_lookup()
234 temp_setup->divr1++) { in clk_sscg_divr1_lookup()
236 do_div(temp_setup->ref_div1, temp_setup->divr1 + 1); in clk_sscg_divr1_lookup()
331 u32 val, divr1, divf1, divr2, divf2, divq; in clk_sscg_pll_recalc_rate() local
335 divr1 = FIELD_GET(PLL_DIVR1_MASK, val); in clk_sscg_pll_recalc_rate()
352 do_div(temp64, (divr1 + 1) * (divr2 + 1) * (divq + 1)); in clk_sscg_pll_recalc_rate()
376 val |= FIELD_PREP(PLL_DIVR1_MASK, setup->divr1); in clk_sscg_pll_set_rate()
/dports/multimedia/libv4l/linux-5.13-rc2/drivers/clk/imx/
H A Dclk-sscg-pll.c72 int divr1, divf1; member
214 do_div(vco1, temp_setup->divr1 + 1); in clk_sscg_divf1_lookup()
233 for (temp_setup->divr1 = 0; temp_setup->divr1 <= PLL_DIVR1_MAX; in clk_sscg_divr1_lookup()
234 temp_setup->divr1++) { in clk_sscg_divr1_lookup()
236 do_div(temp_setup->ref_div1, temp_setup->divr1 + 1); in clk_sscg_divr1_lookup()
331 u32 val, divr1, divf1, divr2, divf2, divq; in clk_sscg_pll_recalc_rate() local
335 divr1 = FIELD_GET(PLL_DIVR1_MASK, val); in clk_sscg_pll_recalc_rate()
352 do_div(temp64, (divr1 + 1) * (divr2 + 1) * (divq + 1)); in clk_sscg_pll_recalc_rate()
376 val |= FIELD_PREP(PLL_DIVR1_MASK, setup->divr1); in clk_sscg_pll_set_rate()
/dports/sysutils/u-boot-chip/u-boot-2021.07/drivers/clk/
H A Dclk_stm32h7.c505 u32 divm1, divn1, divp1, divq1, divr1, fracn1; in stm32_get_PLL1_rate() local
542 divr1 = readl(&regs->pll1divr) & RCC_PLL1DIVR_DIVR1_MASK; in stm32_get_PLL1_rate()
543 divr1 = (divr1 >> RCC_PLL1DIVR_DIVR1_SHIFT) + 1; in stm32_get_PLL1_rate()
552 divm1, divn1, divp1, divq1, divr1); in stm32_get_PLL1_rate()
565 return (vco + rate) / divr1; in stm32_get_PLL1_rate()
/dports/emulators/qemu42/qemu-4.2.1/roms/u-boot/drivers/clk/
H A Dclk_stm32h7.c501 u32 divm1, divn1, divp1, divq1, divr1, fracn1; in stm32_get_PLL1_rate() local
538 divr1 = readl(&regs->pll1divr) & RCC_PLL1DIVR_DIVR1_MASK; in stm32_get_PLL1_rate()
539 divr1 = (divr1 >> RCC_PLL1DIVR_DIVR1_SHIFT) + 1; in stm32_get_PLL1_rate()
548 __func__, divm1, divn1, divp1, divq1, divr1); in stm32_get_PLL1_rate()
561 return (vco + rate) / divr1; in stm32_get_PLL1_rate()
/dports/emulators/qemu5/qemu-5.2.0/roms/u-boot/drivers/clk/
H A Dclk_stm32h7.c501 u32 divm1, divn1, divp1, divq1, divr1, fracn1; in stm32_get_PLL1_rate() local
538 divr1 = readl(&regs->pll1divr) & RCC_PLL1DIVR_DIVR1_MASK; in stm32_get_PLL1_rate()
539 divr1 = (divr1 >> RCC_PLL1DIVR_DIVR1_SHIFT) + 1; in stm32_get_PLL1_rate()
548 __func__, divm1, divn1, divp1, divq1, divr1); in stm32_get_PLL1_rate()
561 return (vco + rate) / divr1; in stm32_get_PLL1_rate()
/dports/sysutils/u-boot-olinuxino-lime/u-boot-2021.07/drivers/clk/
H A Dclk_stm32h7.c505 u32 divm1, divn1, divp1, divq1, divr1, fracn1; in stm32_get_PLL1_rate() local
542 divr1 = readl(&regs->pll1divr) & RCC_PLL1DIVR_DIVR1_MASK; in stm32_get_PLL1_rate()
543 divr1 = (divr1 >> RCC_PLL1DIVR_DIVR1_SHIFT) + 1; in stm32_get_PLL1_rate()
552 divm1, divn1, divp1, divq1, divr1); in stm32_get_PLL1_rate()
565 return (vco + rate) / divr1; in stm32_get_PLL1_rate()
/dports/sysutils/u-boot-olinuxino-lime2/u-boot-2021.07/drivers/clk/
H A Dclk_stm32h7.c505 u32 divm1, divn1, divp1, divq1, divr1, fracn1; in stm32_get_PLL1_rate() local
542 divr1 = readl(&regs->pll1divr) & RCC_PLL1DIVR_DIVR1_MASK; in stm32_get_PLL1_rate()
543 divr1 = (divr1 >> RCC_PLL1DIVR_DIVR1_SHIFT) + 1; in stm32_get_PLL1_rate()
552 divm1, divn1, divp1, divq1, divr1); in stm32_get_PLL1_rate()
565 return (vco + rate) / divr1; in stm32_get_PLL1_rate()
/dports/sysutils/u-boot-olinuxino-lime2-emmc/u-boot-2021.07/drivers/clk/
H A Dclk_stm32h7.c505 u32 divm1, divn1, divp1, divq1, divr1, fracn1; in stm32_get_PLL1_rate() local
542 divr1 = readl(&regs->pll1divr) & RCC_PLL1DIVR_DIVR1_MASK; in stm32_get_PLL1_rate()
543 divr1 = (divr1 >> RCC_PLL1DIVR_DIVR1_SHIFT) + 1; in stm32_get_PLL1_rate()
552 divm1, divn1, divp1, divq1, divr1); in stm32_get_PLL1_rate()
565 return (vco + rate) / divr1; in stm32_get_PLL1_rate()
/dports/sysutils/u-boot-wandboard/u-boot-2021.07/drivers/clk/
H A Dclk_stm32h7.c505 u32 divm1, divn1, divp1, divq1, divr1, fracn1; in stm32_get_PLL1_rate() local
542 divr1 = readl(&regs->pll1divr) & RCC_PLL1DIVR_DIVR1_MASK; in stm32_get_PLL1_rate()
543 divr1 = (divr1 >> RCC_PLL1DIVR_DIVR1_SHIFT) + 1; in stm32_get_PLL1_rate()
552 divm1, divn1, divp1, divq1, divr1); in stm32_get_PLL1_rate()
565 return (vco + rate) / divr1; in stm32_get_PLL1_rate()
/dports/sysutils/u-boot-cubieboard2/u-boot-2021.07/drivers/clk/
H A Dclk_stm32h7.c505 u32 divm1, divn1, divp1, divq1, divr1, fracn1; in stm32_get_PLL1_rate() local
542 divr1 = readl(&regs->pll1divr) & RCC_PLL1DIVR_DIVR1_MASK; in stm32_get_PLL1_rate()
543 divr1 = (divr1 >> RCC_PLL1DIVR_DIVR1_SHIFT) + 1; in stm32_get_PLL1_rate()
552 divm1, divn1, divp1, divq1, divr1); in stm32_get_PLL1_rate()
565 return (vco + rate) / divr1; in stm32_get_PLL1_rate()
/dports/sysutils/u-boot-cubox-hummingboard/u-boot-2021.07/drivers/clk/
H A Dclk_stm32h7.c505 u32 divm1, divn1, divp1, divq1, divr1, fracn1; in stm32_get_PLL1_rate() local
542 divr1 = readl(&regs->pll1divr) & RCC_PLL1DIVR_DIVR1_MASK; in stm32_get_PLL1_rate()
543 divr1 = (divr1 >> RCC_PLL1DIVR_DIVR1_SHIFT) + 1; in stm32_get_PLL1_rate()
552 divm1, divn1, divp1, divq1, divr1); in stm32_get_PLL1_rate()
565 return (vco + rate) / divr1; in stm32_get_PLL1_rate()
/dports/sysutils/u-boot-cubieboard/u-boot-2021.07/drivers/clk/
H A Dclk_stm32h7.c505 u32 divm1, divn1, divp1, divq1, divr1, fracn1; in stm32_get_PLL1_rate() local
542 divr1 = readl(&regs->pll1divr) & RCC_PLL1DIVR_DIVR1_MASK; in stm32_get_PLL1_rate()
543 divr1 = (divr1 >> RCC_PLL1DIVR_DIVR1_SHIFT) + 1; in stm32_get_PLL1_rate()
552 divm1, divn1, divp1, divq1, divr1); in stm32_get_PLL1_rate()
565 return (vco + rate) / divr1; in stm32_get_PLL1_rate()
/dports/sysutils/u-boot-firefly-rk3399/u-boot-2021.07/drivers/clk/
H A Dclk_stm32h7.c505 u32 divm1, divn1, divp1, divq1, divr1, fracn1; in stm32_get_PLL1_rate() local
542 divr1 = readl(&regs->pll1divr) & RCC_PLL1DIVR_DIVR1_MASK; in stm32_get_PLL1_rate()
543 divr1 = (divr1 >> RCC_PLL1DIVR_DIVR1_SHIFT) + 1; in stm32_get_PLL1_rate()
552 divm1, divn1, divp1, divq1, divr1); in stm32_get_PLL1_rate()
565 return (vco + rate) / divr1; in stm32_get_PLL1_rate()
/dports/sysutils/u-boot-a13-olinuxino/u-boot-2021.07/drivers/clk/
H A Dclk_stm32h7.c505 u32 divm1, divn1, divp1, divq1, divr1, fracn1; in stm32_get_PLL1_rate() local
542 divr1 = readl(&regs->pll1divr) & RCC_PLL1DIVR_DIVR1_MASK; in stm32_get_PLL1_rate()
543 divr1 = (divr1 >> RCC_PLL1DIVR_DIVR1_SHIFT) + 1; in stm32_get_PLL1_rate()
552 divm1, divn1, divp1, divq1, divr1); in stm32_get_PLL1_rate()
565 return (vco + rate) / divr1; in stm32_get_PLL1_rate()
/dports/sysutils/u-boot-sinovoip-bpi-m3/u-boot-2021.07/drivers/clk/
H A Dclk_stm32h7.c505 u32 divm1, divn1, divp1, divq1, divr1, fracn1; in stm32_get_PLL1_rate() local
542 divr1 = readl(&regs->pll1divr) & RCC_PLL1DIVR_DIVR1_MASK; in stm32_get_PLL1_rate()
543 divr1 = (divr1 >> RCC_PLL1DIVR_DIVR1_SHIFT) + 1; in stm32_get_PLL1_rate()
552 divm1, divn1, divp1, divq1, divr1); in stm32_get_PLL1_rate()
565 return (vco + rate) / divr1; in stm32_get_PLL1_rate()
/dports/sysutils/u-boot-sopine/u-boot-2021.07/drivers/clk/
H A Dclk_stm32h7.c505 u32 divm1, divn1, divp1, divq1, divr1, fracn1; in stm32_get_PLL1_rate() local
542 divr1 = readl(&regs->pll1divr) & RCC_PLL1DIVR_DIVR1_MASK; in stm32_get_PLL1_rate()
543 divr1 = (divr1 >> RCC_PLL1DIVR_DIVR1_SHIFT) + 1; in stm32_get_PLL1_rate()
552 divm1, divn1, divp1, divq1, divr1); in stm32_get_PLL1_rate()
565 return (vco + rate) / divr1; in stm32_get_PLL1_rate()
/dports/sysutils/u-boot-a64-olinuxino/u-boot-2021.07/drivers/clk/
H A Dclk_stm32h7.c505 u32 divm1, divn1, divp1, divq1, divr1, fracn1; in stm32_get_PLL1_rate() local
542 divr1 = readl(&regs->pll1divr) & RCC_PLL1DIVR_DIVR1_MASK; in stm32_get_PLL1_rate()
543 divr1 = (divr1 >> RCC_PLL1DIVR_DIVR1_SHIFT) + 1; in stm32_get_PLL1_rate()
552 divm1, divn1, divp1, divq1, divr1); in stm32_get_PLL1_rate()
565 return (vco + rate) / divr1; in stm32_get_PLL1_rate()
/dports/sysutils/u-boot-qemu-arm64/u-boot-2021.07/drivers/clk/
H A Dclk_stm32h7.c505 u32 divm1, divn1, divp1, divq1, divr1, fracn1; in stm32_get_PLL1_rate() local
542 divr1 = readl(&regs->pll1divr) & RCC_PLL1DIVR_DIVR1_MASK; in stm32_get_PLL1_rate()
543 divr1 = (divr1 >> RCC_PLL1DIVR_DIVR1_SHIFT) + 1; in stm32_get_PLL1_rate()
552 divm1, divn1, divp1, divq1, divr1); in stm32_get_PLL1_rate()
565 return (vco + rate) / divr1; in stm32_get_PLL1_rate()
/dports/sysutils/u-boot-rpi/u-boot-2021.07/drivers/clk/
H A Dclk_stm32h7.c505 u32 divm1, divn1, divp1, divq1, divr1, fracn1; in stm32_get_PLL1_rate() local
542 divr1 = readl(&regs->pll1divr) & RCC_PLL1DIVR_DIVR1_MASK; in stm32_get_PLL1_rate()
543 divr1 = (divr1 >> RCC_PLL1DIVR_DIVR1_SHIFT) + 1; in stm32_get_PLL1_rate()
552 divm1, divn1, divp1, divq1, divr1); in stm32_get_PLL1_rate()
565 return (vco + rate) / divr1; in stm32_get_PLL1_rate()
/dports/sysutils/u-boot-nanopi-r4s/u-boot-2021.07/drivers/clk/
H A Dclk_stm32h7.c505 u32 divm1, divn1, divp1, divq1, divr1, fracn1; in stm32_get_PLL1_rate() local
542 divr1 = readl(&regs->pll1divr) & RCC_PLL1DIVR_DIVR1_MASK; in stm32_get_PLL1_rate()
543 divr1 = (divr1 >> RCC_PLL1DIVR_DIVR1_SHIFT) + 1; in stm32_get_PLL1_rate()
552 divm1, divn1, divp1, divq1, divr1); in stm32_get_PLL1_rate()
565 return (vco + rate) / divr1; in stm32_get_PLL1_rate()
/dports/sysutils/u-boot-olimex-a20-som-evb/u-boot-2021.07/drivers/clk/
H A Dclk_stm32h7.c505 u32 divm1, divn1, divp1, divq1, divr1, fracn1; in stm32_get_PLL1_rate() local
542 divr1 = readl(&regs->pll1divr) & RCC_PLL1DIVR_DIVR1_MASK; in stm32_get_PLL1_rate()
543 divr1 = (divr1 >> RCC_PLL1DIVR_DIVR1_SHIFT) + 1; in stm32_get_PLL1_rate()
552 divm1, divn1, divp1, divq1, divr1); in stm32_get_PLL1_rate()
565 return (vco + rate) / divr1; in stm32_get_PLL1_rate()
/dports/sysutils/u-boot-nanopi-m1plus/u-boot-2021.07/drivers/clk/
H A Dclk_stm32h7.c505 u32 divm1, divn1, divp1, divq1, divr1, fracn1; in stm32_get_PLL1_rate() local
542 divr1 = readl(&regs->pll1divr) & RCC_PLL1DIVR_DIVR1_MASK; in stm32_get_PLL1_rate()
543 divr1 = (divr1 >> RCC_PLL1DIVR_DIVR1_SHIFT) + 1; in stm32_get_PLL1_rate()
552 divm1, divn1, divp1, divq1, divr1); in stm32_get_PLL1_rate()
565 return (vco + rate) / divr1; in stm32_get_PLL1_rate()
/dports/sysutils/u-boot-nanopi-neo/u-boot-2021.07/drivers/clk/
H A Dclk_stm32h7.c505 u32 divm1, divn1, divp1, divq1, divr1, fracn1; in stm32_get_PLL1_rate() local
542 divr1 = readl(&regs->pll1divr) & RCC_PLL1DIVR_DIVR1_MASK; in stm32_get_PLL1_rate()
543 divr1 = (divr1 >> RCC_PLL1DIVR_DIVR1_SHIFT) + 1; in stm32_get_PLL1_rate()
552 divm1, divn1, divp1, divq1, divr1); in stm32_get_PLL1_rate()
565 return (vco + rate) / divr1; in stm32_get_PLL1_rate()
/dports/sysutils/u-boot-nanopi-neo-air/u-boot-2021.07/drivers/clk/
H A Dclk_stm32h7.c505 u32 divm1, divn1, divp1, divq1, divr1, fracn1; in stm32_get_PLL1_rate() local
542 divr1 = readl(&regs->pll1divr) & RCC_PLL1DIVR_DIVR1_MASK; in stm32_get_PLL1_rate()
543 divr1 = (divr1 >> RCC_PLL1DIVR_DIVR1_SHIFT) + 1; in stm32_get_PLL1_rate()
552 divm1, divn1, divp1, divq1, divr1); in stm32_get_PLL1_rate()
565 return (vco + rate) / divr1; in stm32_get_PLL1_rate()

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