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Searched refs:edif_cellref_logic (Results 1 – 1 of 1) sorted by relevance

/dports/cad/iverilog/verilog-11.0/tgt-fpga/
H A Dxilinx.c502 static void edif_cellref_logic(ivl_net_logic_t net, const char*def) in edif_cellref_logic() function
598 edif_cellref_logic(net, cellref_attribute); in xilinx_logic()